Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2000-06-26
2003-09-30
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S572000, C345S561000, C710S022000
Reexamination Certificate
active
06628289
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a rendering apparatus and method for, e.g., a printer which forms an image on a bitmap memory and prints the image, and a storage medium that stores a program for implementing the rendering method on a computer.
BACKGROUND OF THE INVENTION
Conventionally, a rendering apparatus of this type processes in turn a series of operations for reading data on a bitmap memory, logically operating the read data and a generated source image, and writing back the logic operation result at an identical address on the bitmap memory. Upon completion of those operations, the apparatus repeats similar processes.
However, since logic operations come to a halt upon reading data from the bitmap memory or upon writing data on the bitmap memory, and access to the bitmap memory also comes to a halt during execution of logic operations, the image formation efficiency is poor, and high-speed rendering cannot be realized.
SUMMARY OF THE INVENTION
The present invention has been proposed to solve the conventional problems, and has as its object to provide a rendering apparatus for forming an image on a bitmap memory by logically operating a source image and data on the bitmap memory, comprising image generation means for generating the source image, address generation means for generating read and write addresses of the bitmap memory, DMA read means for directly reading out data from the bitmap memory in accordance with the generated address, input data holding means for holding the data read from the bitmap memory, logic operation means for making a logic operation on the basis of the read data and data of the source image, output data holding means for holding the logically operated data, and DMA write means for writing the data held in the bitmap memory in accordance with the generated address, wherein a data input process for reading out data from the bitmap memory and holding that data in the input data holding means, the logic operation, and an output process for writing the logic operation result at a predetermined address of the bitmap memory are synchronously processed parallel to each other.
According to a preferred aspect of the present invention, in the rendering apparatus, the address generation means generates successive addresses when data that undergoes a logic operation process executed at the time of the next data input process is not last data of the current line, and generates an address of the next line when the data that undergoes the logic operation process is the last data of the current line.
According to a preferred aspect of the present invention, the rendering apparatus further comprises a plurality of data holding means for holding input or output data, and process latency due to data storage means which is not empty is removed by selectively using the plurality of data holding means as output or input data holding means.
According to a preferred aspect of the present invention, the rendering apparatus further comprises a plurality of input and output data holding means corresponding to a plurality of data processing units, and a high-speed rendering process is achieved by simultaneously processing the plurality of data processing units.
Alternatively, a rendering method for forming an image on a bitmap memory by logically operating a source image and data on the bitmap memory, comprises the image generation step of generating the source image, the address generation step of generating read and write addresses of the bitmap memory, the DMA read step of directly reading out data from the bitmap memory in accordance with the generated address, the input data holding step of holding the data read from the bitmap memory in an input memory, the logic operation step of making a logic operation on the basis of the read data and data of the source image, the output data holding step of holding the logically operated data in an output memory, and the DMA write step of writing the data held in the output memory in the bitmap memory in accordance with the generated address, wherein a data input process for reading out data from the bitmap memory and holding that data in the input memory, the logic operation, and an output process for writing the logic operation result at a predetermined address of the bitmap memory are synchronously processed parallel to each other.
According to a preferred aspect of the present invention, in the rendering method, the address generation step includes the step of generating successive addresses when data that undergoes a logic operation process executed at the time of the next data input process is not last data of the current line, and generating an address of the next line when the data that undergoes the logic operation process is the last data of the current line.
According to a preferred aspect of the present invention, in the rendering method, a plurality of memories for holding data are provided, and process latency due to a memory which is not empty is removed by selectively using the plurality of memories as output or input memory.
According to a preferred aspect of the present invention, in the rendering method, a plurality of input and output memories corresponding to a plurality of data processing units are provided, and a high-speed rendering process is achieved by simultaneously processing the plurality of data processing units.
Alternatively, a storage medium that stores a rendering program for forming an image on a bitmap memory by logically operating a source image and data on the bitmap memory, the program comprises a code of the image generation step of generating the source image, a code of the address generation step of generating read and write addresses of the bitmap memory, a code of the DMA read step of directly reading out data from the bitmap memory in accordance with the generated address, a code of the input data holding step of holding the data read from the bitmap memory in an input memory, a code of the logic operation step of making a logic operation on the basis of the read data and data of the source image, a code of the output data holding step of holding the logically operated data in an output memory, and a code of the DMA write step of writing the data held in the output memory in the bitmap memory in accordance with the generated address, wherein a data input process for reading out data from the bitmap memory and holding that data in the input memory, the logic operation, and an output process for writing the logic operation result at a predetermined address of the bitmap memory are synchronously processed parallel to each other.
According to a preferred aspect of the present invention, in the storage medium, the code of the address generation step includes the step of generating successive addresses when data that undergoes a logic operation process executed at the time of the next data input process is not last data of the current line, and generating an address of the next line when the data that undergoes the logic operation process is the last data of the current line.
REFERENCES:
patent: 4920480 (1990-04-01), Murakami et al.
patent: 5218674 (1993-06-01), Peaslee et al.
patent: 5329615 (1994-07-01), Peaslee et al.
patent: 5911147 (1999-06-01), Onodera et al.
Bella Matthew C.
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Nguyen Hau
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