Remultipelxer cache architecture and memory organization for sto

Details Remultipelxer cache architecture and memory organization for sto Remultipelxer cache architecture and memory organization for sto

1998-01-14

2000-05-16

Kizou, Hassan

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370535, H04L 1256

Patent

active

060646764

ABSTRACT:
A method and system are provided for remultiplexing program bearing data. The remultiplexing method and system are applicable to MPEG-2 compliant transport streams carrying video programs. A descriptor based system is used for scheduling the timely output of transport packets wherein each descriptor records a dispatch time as well as a receipt time for each transport packet. The receipt time is used for estimating program clock reference adjustments, but final program clock reference adjustment is performed in hardware in relation to the precise output timing of each transport packets. A descriptor and transport packet caching technique is used for decoupling the synchronous receipt and transmission of transport packets from any asynchronous processing performed thereon. The descriptors can also be used for managing scrambling and descrambling control words (encryption and decryption keys). Remultiplexing functions may be distributed across a network. The remultiplexer can furthermore optimize the bandwidth of transport streams by replacing null transport packets with transport packet data to be inserted into the output transport stream. Program data transmitted via asynchronous communication links is re-timed and assistance is provided for outputting program data on such asynchronous communication links to reduce a variation in end-to-end delay incurred by the program data. Remultiplexing and program specific information can be seamlessly dynamically varied without stopping, or introducing a discontinuity in, the flow of outputted transport packets. A technique is also provided for locking multiple internal reference clock generators.

REFERENCES:
patent: 5420866 (1995-05-01), Wasilewski
patent: 5517250 (1996-05-01), Hoogenboom et al.
patent: 5535209 (1996-07-01), Glasser et al.
patent: 5561791 (1996-10-01), Mendelson et al.
patent: 5640388 (1997-06-01), Woodhead et al.
patent: 5652627 (1997-07-01), Allen
patent: 5691986 (1997-11-01), Pearlstein
patent: 5754783 (1998-05-01), Mendelson et al.
patent: 5801781 (1998-09-01), Hiroshima et al.
patent: 5835493 (1998-11-01), Magee et al.

Affiliated with

Also associated with

Rating

Remultipelxer cache architecture and memory organization for sto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Remultipelxer cache architecture and memory organization for sto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Remultipelxer cache architecture and memory organization for sto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-265171