Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-07-14
2003-05-20
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S712000, C438S723000, C438S724000
Reexamination Certificate
active
06566269
ABSTRACT:
The present invention relates to processing of semiconductor wafers using a plasma etching process and, more particularly, to a method for removing contaminants from a photoresist layer on such wafers.
BACKGROUND OF THE INVENTION
Manufacture of an integrated circuit device involves numerous process steps to create active and passive devices on a semiconductor substrate, to create conductive leads for connecting such devices and to create conductive pads for external connection to the completed device. In the fabrication of semiconductor components, the various devices are formed in layers upon an underlying substrate typically composed of silicon, germanium, or gallium arsenide. Metal conductor lines form interconnects between the various discrete devices. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In general, areas to be etched or removed are defined by lithographic patterns outlined by a carbon containing photoresist layer on an exposed surface of the device. Etching is achieved by exposing the photoresist covered layer to a chemical compound that will desolve a layer to be removed but which compound will not attack the photoresist. In many processes for device fabrication, a pattern defined by the lithographic technique is transferred through a layer of material formed on the surface of a substrate. Typically, the pattern is transferred by etching using a plasma. The term plasma, as used in this disclosure, refers to a partially ionized gas consisting of positively and negatively charged molecular species, as well as neutrals.
Plasma etching processes are typically performed in an apparatus such as a plasma reactor. Plasma reactors generally include a reaction chamber, a plasma generating system, a wafer holder and handling system and a gas delivery system (i.e. inlet, exhaust and flow control). The term reaction chamber, as used in this disclosure, refers to the area within a plasma reactor where ionized gases physically and/or chemically interact with a material layer formed on the surface of a substrate.
A cross-sectional view of an example of a plasma reactor, called a parallel plate reactor
10
is shown in FIG.
1
. Parallel plate reactor
10
includes two electrodes
11
,
12
positioned parallel to each other in a reaction chamber
14
. Substrates
15
with lithographically defined patterns (not shown) formed thereon are placed on the surface
12
a
of electrode
12
. In a typical etching process using a plasma reactor such as a parallel plate reactor
10
, gases are mixed and introduced into the reaction chamber
14
. The mixed gases flow between electrodes
11
,
12
. An electric field applied between electrodes
11
,
12
ionizes the gases and forms a plasma
13
. The plasma
13
then etches the layer of material (not shown) formed on the surface of substrates
15
and transfers the lithographically defined pattern therethrough.
FIGS. 2A through 2C
are diagrammatic cross-sectional views depicting exemplary processing steps involved in constructing an integrated circuit device with post contact and via holes. In
FIG. 2A
, there is shown a semiconductor substrate
16
, having disposed thereon a plurality of transistors or diodes, shown generally as active regions
22
. A first dielectric layer
24
is deposited over the substrate, which may be comprised of a thin film of silicon-dioxide, SiO.sub.2, or other dielectric materials such as a-Ta.sub.2 O.sub.5, a-TiO.sub.x, or x-(Ba,Sr)TiO.sub.3. An etch stop layer
26
comprised, for example, of silicon nitride, may be deposited over the dielectric layer. Contact holes
28
(shown in
FIG. 2C
) are formed in the device of
FIG. 2A
to provide contact with the active regions
22
of the substrate
16
. The etching of the device to form the contact holes
28
often is performed with a photoresist mask and dry etching process involving use of a plasma RIE process and a reactive gas, such as CHF.sub.3 or SF.sub.6. Referring to
FIG. 2B
, a photosensitive mask may be used to deposit a photoresist layer
20
, over selected regions of the etch stop layer
16
. The exposed portions of the etch stop layer
26
and dielectric layer
24
are controllably etched with the reactive etchant to expose the active regions
22
and provide contact holes
28
(FIG.
2
C).
One of the latter steps in fabrication of the semiconductor integrated circuit is the formation of bonding pads which enable connection of the integrated circuit to an external device, i.e., the bonding pads create a connection point for electrical conductors. Bonding pads are formed by deposition of a conductive material layer at desired areas of an integrated circuit, typically by successively depositing a patterned conductive material layer, a dielectric material layer and a passivation material layer, followed by patterned etching of the passivation and dielectric layers, providing an exposed surface of the conductive material. Etching is performed in the plasma chamber using gases such as SF
6
, CHF
3
, and CF
4
, to etch silicon nitride (Si
3
N
4
), silicon dioxide (SiO
2
) and titanium nitrate (TiN), respectively. During bond pad etching, the semiconductor wafer surface is covered with a photoresist layer to prevent etching at areas other than the bond pads. The etching process releases fluorine and sulfur which contaminate the photoresist layer. When the wafer is removed from the plasma chamber and exposed to ambient conditions, the wafers outgas the fluorine and sulfur which then combine with moisture in the air to form SO
2
and HF. Since the wafers are placed in a protective wafer box upon removal from the plasma chamber, these gases are trapped in the box until opened by a human operator. The operator is then exposed to an obnoxious smell. More importantly, these gases may corrode or formed an oxide layer on the bonding pads that can adversely effect electrical continuity when electrical conductors are subsequently attached. Accordingly, it would be desireable to provide a method for neutralizing or removing the gas contaminants before exposure to ambient conditions.
SUMMARY OF THE INVENTION
The above described detriments of the prior art are addressed in one embodiment of the present invention by providing a method for effecting outgassing of contaminants from semiconductor wafers immediately subsequent to plasma etching of such wafers. In an exemplary form, the invention is illustrated in a plasma etch process for wafer bonding pads in which fluorine and sulfur ions are trapped as contaminants in a photoresist layer of the wafer. The inventive process comprises exhausting of the etchant gases from the plasma chamber and introducing a mixture of argon and oxygen at a controlled rate and pressure so that the fluorine and sulfur outgas in the plasma chamber prior to removal of the wafer therefrom. More particularly, power is applied to the reactor to create a plasma of at least some of the argon and oxygen gases such that the resultant Ar
−
and O
+
ions bombard the photoresist surface and remove at least an outer portion in which a majority of the fluorine and sulfur ions are entrapped. The fluorine and sulfur ions are then exhausted from the reactor with the argon and oxygen, combining with carbon ions from the photoresist and oxygen ions to form CF
2
and SO
2
.
In one embodiment, the argon/oxygen mixture is flowed in the plasma chamber for a time period of about 10 seconds at a pressure of about 100 mTorr and a power level of 500 watts but without a magnetic field. The argon gas is flowed at about 50 sccm and the oxygen is flowed at about 18 sccm.
REFERENCES:
patent: 5015330 (1991-05-01), Okumura et al.
patent: 5135608 (1992-08-01), Okutani
patent: 5227001 (1993-07-01), Tamaki et al.
pat
Biles Peter J.
Luque Sylvia M.
Mills Robert H.
Nelson Lauri M.
Pita Mario V.
Kunemund Robert
Lucent Technologies - Inc.
Umez-Erenini Lynette J.
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