Remote data link address sequencer and a memory arrangement for

Details Remote data link address sequencer and a memory arrangement for Remote data link address sequencer and a memory arrangement for

1983-12-22

1986-01-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 89, 370 66, H04J 110, H04J 308, H04J 316, H04Q 1100

Patent

active

045649375

ABSTRACT:
An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

REFERENCES:
patent: Re29450 (1977-10-01), Goldsby et al.
patent: 3956593 (1976-05-01), Collins et al.
patent: 4309765 (1982-01-01), Mueller et al.
Hannaford, "Sequentially Addressed Storage", IBM Tech. Disclosure Bulletin, vol. 20, No. 2, Jul. 1977, pp. 732-733.

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