Pulse or digital communications – Synchronizers
Reexamination Certificate
2006-06-01
2009-12-22
Ha, Dac V (Department: 2611)
Pulse or digital communications
Synchronizers
C375S231000, C375S233000, C375S344000, C375S350000
Reexamination Certificate
active
07636408
ABSTRACT:
An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.
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Bau Jason H.
Doblar Drew G.
Risk Gabriel C.
Ha Dac V
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Rankin Rory D.
Sun Microsystems Inc.
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