Reliable edge cell array design

Details Reliable edge cell array design Reliable edge cell array design

1995-05-31

1998-03-24

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

257204, 257390, 257443, 257494, 257495, 257923, 257925, H01L 2710

Patent

active

057316066

ABSTRACT:
Techniques are provided for protecting the cells of an array against deleterious effects of, for example, photolithography, etching and charge contamination. The cell array is designed to have edge cells modified at layout, or inactive edge cells, or guardrings surrounding the active array to contain the above effects, leaving the active cells highly reliable and with identical behavior.

REFERENCES:
patent: 5051917 (1991-09-01), Gould et al.
patent: 5184204 (1993-02-01), Mihara et al.
patent: 5545915 (1996-08-01), Disney et al.

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