Reliable aluminum interconnect via structures

Details Reliable aluminum interconnect via structures Reliable aluminum interconnect via structures

1998-08-13

2001-10-02

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000

Reexamination Certificate

active

06297557

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to reliable interconnect via structures and methods for making the same.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor (“MOS”) devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as MOS transistors.
Conventionally, a dielectric layer (e.g., silicon oxide) is deposited over the devices, and via holes are patterned and formed through the dielectric layer to the devices below. As is well known in the art, photolithography “patterning” is typically accomplished by depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a resist via mask, and etching the exposed dielectric layer to form via holes leading to a lower level. Once the via holes are formed, a conductive material such as tungsten is used to fill the via holes to define what are known as “W” tungsten plugs. Once the, tungsten plugs are formed, a metallization layer is formed over the dielectric layer and the tungsten plugs. The metallization layer is then patterned using conventional photolithography techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of metallization lines are desired.
Recently, to reduce via resistance and increase device speeds, designers have been filling the via holes with aluminum “Al”, and using low “K” dielectric materials for the intermetal dielectric layers. The aluminum filled via holes (i.e., aluminum plugs) and the low “K” dielectric materials have been successful in decreasing resistance in interconnect structures, but a substantial amount of aluminum atoms within the aluminum plugs have been found to migrate along with the flow of electrons. This electron flow therefore causes the formation of voids in the interconnect lines as well as in the aluminum plugs.
To illustrate this problem,
FIG. 1
shows a cross-section of a semiconductor substrate
10
having a plurality of conventionally fabricated layers. The semiconductor substrate
10
may include diffusion regions
12
and a polysilicon gate
14
formed over the semiconductor substrate
10
. A first dielectric layer
19
is formed over the semiconductor substrate
10
and is then planarized. Once planarized, via holes are formed through the first dielectric layer
19
, and an aluminum plug
16
is defined after a chemical vapor deposition (CVD) aluminum deposition. Next, a metallization layer is deposited and patterned over the first dielectric layer to define a first level of interconnect lines
24
. The process is again repeated to form a second dielectric layer
22
, aluminum plugs
18
a
and
18
b
, and a second level of interconnect lines
26
Once the structure is complete, current “I” may be passed through the interconnect structure formed by the first and second levels of interconnect lines
24
and
26
, and the aluminum plugs
18
a
and
18
b
. Therefore, when current flows that are typical in interconnect buses, power lines “Vdd” and ground lines “Vss” are passed through this low resistive structure, the electron flow “e” may unfortunately cause voids
32
in the aluminum plug
18
a
and voids
30
and
30
′ in the interconnect lines
24
and
26
, respectively. It is believed that the voids
32
in the aluminum plug
18
a
is partially due to the fact that less aluminum material is contained within the via holes as compared to the interconnect line itself. By way of example, a typical aluminum plug may contain a volume of about 0.75 microns
3
of aluminum, while a typical metallization interconnect line lying over an aluminum plug may contain a volume of about 3.2 microns
3
.
Accordingly, when the current flow begins to cause electromigration of aluminum atoms in the interconnect structure of
FIG. 1
, an “open circuit” failure will necessarily tend to occur much more rapidly within the aluminum plug
18
a
. In practice, given the above exemplary aluminum plug and interconnect volumes, aluminum plugs may cause device failures within about 1 to 2 years of use, while the electromigration in the interconnect line may not cause a device failure for more than about 10 years. However, a device is only as reliable as its weakest link, and therefore, even though the interconnect lines can withstand more severe voids due to electromigration, the aluminum plugs will unfortunately cause the entire device to fail at a much faster rate, thereby producing a less reliable device.
Another interconnect problem that has recently caused designers substantial difficulties is accidental over-etching of aluminum plugs when a misalignment occurs in the photolithography process. As shown in
FIG. 1
, when the metallization layer that is patterned to form the second interconnect layer
26
is misaligned, the underlying aluminum plug
18
a
is left exposed to the etching steps that are used to pattern the second interconnect layer
26
. Because the aluminum plug
18
a
is essentially the same type of aluminum-based material used for the second interconnect layers
26
, the etching chemistries used will also attack the aluminum plug
18
a
. When this happens, a gap
40
is may be etched into the aluminum plug
18
a
, which may enable process chemicals and moisture to be trapped therein. Of course, when chemicals or moisture are trapped within gap
40
, aluminum plug failures may arise due to corrosion and vapor energy releasing explosions during subsequent high temperature operations. For more information on vapor energy releasing explosions, reference may be made to a commonly assigned U.S. patent application Ser. No. 08/856,949, filed on May 15, 1997 and having inventors Subhas Bothra and Ling Q. Qian. This application is incorporated by reference herein.
Accordingly, in view of the foregoing, there is a need for a highly reliable aluminum plug technology that assists in decreasing interconnect resistance while preventing aluminum plug failing voids. Further yet, there is a need for an aluminum plug technology that prevents destructive gaps in the aluminum plugs due to photolithography misalignments.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing highly reliable aluminum plugs for high speed interconnect structures that prevent aluminum atoms from migrating out of the via holes and thereby causing device damaging short circuit voids. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making a semiconductor interconnect structure is disclosed. The semiconductor interconnect structure includes a semiconductor substrate having an overlying first low K dielectric material. The first low K dielectric material supports a patterned first level of metallization, and a second low K dielectric material overlies the first low K dielectric material and the patterned first level of metallization. The method includes forming at least one via hole through the second low K dielectric material down to the patterned first level of metallization. Depositing a seed layer over the second low K dielectric material and in the at least one via hole. Depositing an aluminum layer over the seed layer that overlies the second low K dielectric material and the at least one via hole such that the at least one via hole is an aluminum filled via hole. Removing

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