Reliability of random access memory systems

Details Reliability of random access memory systems Reliability of random access memory systems

1974-04-01

1976-09-28

Wise, Edward J.

Communications: electrical

Digital comparator systems

340173R, 235153AK, G06F 1100, G11C 1100

Patent

active

039835375

ABSTRACT:
A digital memory is configured as a hierarchical system with at least three levels. The first level consists of a main bus and interfacing for one or more main memory units; the second level consists of a separate second level bus in each main memory unit with a plurality of memory frames independently interfaced to each bus; and the third level consists of a separate third level bus in each memory frame with a plurality of memory storage blocks independently interfaced to each bus. Virtual addressing is employed in which the whole of each address is decoded in the individual memory block which includes for the purpose soft-ware settable registers containing identification numbers.

REFERENCES:
patent: 3585605 (1971-06-01), Gardner et al.
patent: 3633175 (1972-01-01), Harper
patent: 3753242 (1973-08-01), Townsend
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 3755791 (1973-08-01), Arzubi
patent: 3781826 (1973-12-01), Beausoleil
patent: 3803560 (1974-08-01), De Voy et al.
patent: 3821715 (1974-06-01), Hoff, Jr. et al.

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