Relaxed write timing for a memory device

Details Relaxed write timing for a memory device Relaxed write timing for a memory device

1999-06-17

2001-10-30

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080, C711S169000

Reexamination Certificate

active

06310820

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory devices and systems which use memory devices and, more particularly, to the structure and operation of a memory device that uses relaxed write timing.
2. Description of the Related Art
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Not only does the microprocessor access a memory device to retrieve the program instructions, it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a wide variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. One common type of memory device is known as a random access memory (RAM). As the name implies, any memory location in a RAM may be accessed individually to store information or to read information. As a further advantage, the memory cells used in most RAMs are capable of handling millions of write, read, and erase cycles, commonly referred to as programming cycles, without failure.
The two most common and versatile types of RAMs are the dynamic RAM (DRAM) and the static RAM (SRAM). A memory cell of a typical DRAM is formed by a single capacitor and a single transistor. Digital information is stored in the form of a charge on the capacitor, and the transistor permits the capacitor to be accessed for charge storage (writing) or charge detection (reading). Because of this simple memory cell configuration, DRAM memory cells may be densely packed together to form single chip memories having extremely high capacities, currently approaching one gigabyte. Disadvantageously, however, the charge on the memory capacitors tends to diminish rather quickly, requiring periodic refresh cycles. Also, because the stored charge is quite small, relatively complex signal detection and amplification circuitry is used to access the memory cells, thus providing somewhat slower access times than comparable SRAMs.
The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. To understand the advantages and disadvantages, it should first be understood that a typical SRAM memory cell includes a four transistor-latch that stores information and two transistors that permit access for reading or writing information in the latch. The main disadvantage relates to the size of the memory cell required by the six transistors. Because of their size, SRAM memory cells cannot be packed as densely as DRAM memory cells. Therefore, the capacity of a single chip SRAM has not yet, and will probably never, reach the capacity of a single chip DRAM.
However, the superior performance of SRAMs derives from the larger signal stored in the latch and the absence of a need to refresh the stored information. As a result, the signal detection and amplification circuitry used in SRAMs is far simplier, easier to use, and offers higher access speeds. In regard to the access speeds, most current SRAM designs typically exhibit access times of a few nanoseconds to a few tens of nanoseconds. Even though such speeds are superior to most other comparable memories that are currently commercially available, even greater speeds would certainly be desirable.
The present invention may address one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a method of accessing a memory array of a memory device. The method includes the steps of: (a) reading an address into the memory device during a first write cycle; (b) reading data into the memory device during a second write cycle; and (c) delivering the address and the data to the memory array during a third write cycle.
In accordance with another aspect of the present invention, there is provided a method of accessing a memory array of a memory device. The method includes the steps of: (a) setting up an address for delivery to the memory array during a first and a second write cycle; (b) setting up data for delivery to the memory array during the second write cycle; and (c) delivering the address and data to the memory array during a third write cycle.
In accordance with still another aspect of the present invention, there is provided a method of accessing a memory array of a memory device. The method includes the steps of: (a) generating a write clock signal in response to a system clock signal and a write signal; (b) generating a write pulse signal in response to the write clock signal; (c) generating an end-of-write signal in response to the write clock signal and the write pulse signal; (d) storing an address in a first address register in response to the system clock signal; (e) transferring the address from the first address register to a second address register in response to the write clock signal; (f) transferring the address from the second address register to a third address register in response to one of the end-of-write signal and the write clock signal; (g) delivering the address from the third address register to the memory array in response to the write pulse signal; (h) storing data in a first data register in response to the write clock signal; (i) transferring the data from the first data register to a second address register in response to one of the end-of-write signal and the write clock signal; and (j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
In accordance with yet another aspect of the present invention, there is provided a memory device. The memory device includes a write clock signal generator that delivers a write clock signal in response to a system clock signal and a write signal. A write pulse generator delivers a write pulse signal in response to the write clock signal, and an end-of-write signal generator delivers an end-of-write signal in response to the write clock signal and the write pulse signal. A first address register stores an address in response to the system clock signal. A second address register is coupled to the first address register. The first address register transfers the address to the second address register in response to the write clock signal. A third address register is coupled to the second address register. The second address register transfers the address to the third address register in response to one of the end-of-write signal and the write clock signal. A memory array is coupled to the third address register. The third address register transfers the address to the memory array in response to the write pulse signal. A first data register stores data in response to the write clock signal. A second data register is coupled to the first data register. The first data register transfers the data to the second address register in response to one of the end-of-write signal and the write clock signal. A write driver is coupled to the second data register. The second address register transfers the data to the write driver in response to the write pulse signal, and the write driver delivers the data to the memory array.


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