Regulation of current through depletion devices in a MOS integra

Details Regulation of current through depletion devices in a MOS integra Regulation of current through depletion devices in a MOS integra

1979-09-10

1981-08-11

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, H03K 301

Patent

active

042836425

ABSTRACT:
A substrate bias generator is controlled by a comparison circuit to regulate current through depletion devices in a MOS integrated circuit containing a plurality of given depletion devices having a given size and a given pinch-off voltage characteristic on a common substrate. The substrate bias generator is coupled to the substrate for pumping the substrate negatively to lower the effective pinch-off voltage of the given depletion devices, and thereby decrease the current through the given depletion devices. One of the given depletion devices has its source and gate connected to a first node. A reference device is connected to a second node for defining a reference voltage at the second node. The comparison circuit is connected to the first and second nodes for comparing the respective voltages at the first and second nodes and for providing a control signal when the voltage at the first node is not greater than the voltage at the second node. The comparison circuit is further coupled to the substrate bias generator for turning off the substrate bias generator while the control signal is provided. A resistance is connected to the first node in series with the given depletion device that is connected thereto for defining the level of current flow through the given depletion devices at which the substrate bias generator is turned off, to thereby regulate the current flow at such level.

REFERENCES:
patent: T954006 (1977-01-01), Lee et al.
patent: 3609414 (1971-09-01), Pleshko
patent: 4100437 (1978-07-01), Hoff

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