Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-27
2004-11-23
Audong, Gene N. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185120, C365S189070
Reexamination Certificate
active
06822905
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for locally regulating the source terminal voltage in a non-volatile memory cell during the cell programming and/or reading phases. More particularly, the invention relates to a method for locally regulating the source terminal voltage in a non-volatile memory cell during the cell programming and/or reading phases, wherein the voltage is applied by a program-load circuit connected in a conduction path used for transferring a predetermined voltage value to at least one terminal of the memory cell. The invention further relates to a program-load circuit which is incorporated in an electronic semiconductor-integrated memory device comprising an array of non-volatile memory cells, with each of the cells including at least one floating gate transistor having source, drain, gate, and body terminals, and each program-load circuit being connected in a conduction path used for transferring a predetermined voltage value to a terminal of the memory cell.
BACKGROUND OF THE INVENTION
As it is well known in this field of application, a pressing demand for high-density non-volatile memory semiconductors, e.g. flash EEPROMs, from a world-wide semiconductor market has lead to the study and the application of the so-called multi-level memory devices, wherein each memory cell can store more than one bit. Each bit is associated with a predetermined logic level, and the logic levels can be recognized by memory cells having several threshold voltages.
The skilled persons in the art will appreciate that an increased number of threshold voltage levels places stricter demands on the operations to be carried out on the cells, viz. the cell erasing, programming, and reading operations. Reliability considerations place the assigned range reserved for the 2
n−
1 distributions (all of them except for the most programmed one) of a multi-level non-volatile memory cell having n bits/cell at less than 4.5-5V. Consequently, both the width of the threshold distributions and their separation margins become smaller.
FIG. 1
of the accompanying drawings is a comparative plot of the threshold voltage distribution in a conventional two-level (two bits per cell) memory cell and in a multi-level memory with three bits per cell.
As a result, a series of phenomena are faced during the fabrication of multi-level memory devices that would be of trivial import for conventional two-level memories. To make the aspects of this invention more clearly understood, the phases for programming multi-level flash memories will be reviewed here below.
A flash cell read operation includes varying the threshold voltage of the cell by a desired amount. This is achieved by a build-up of electrons in the floating gate region. Shown in
FIG. 2
are some straight lines that represent the characteristic relation of the voltage applied to the gate terminal of a memory cell with the threshold skip that results from varying the voltages applied to the drain terminal of the cell.
To program the cell and obtain threshold voltage distributions with sufficient precision to yield the multi-level feature, the voltage applied to the control gate terminal may be varied stepwise from a minimum to a maximum value. Under optimum gate terminal conditions, the width of each voltage step is equal to the threshold skip sought.
The use of a stepwise gate voltage brings about a timing problem, if the program operation is to be completed in an effective manner. A large number of cells should be programmed in parallel, to minimize program time. Parallel programming is implemented by an algorithm, called “program & verify”, in the course of whose execution each program pulse is followed by a step of reading the cells being programmed to check if they did or did not attain the threshold value.
Any programming pulses will be delivered to properly programmed cells, while cells that have not reached a desired threshold yet will be re-programmed using the same algorithm. Program-load circuits are used for this purpose that allow predetermined program voltage values to be selectively applied to the drain terminals of cells to be programmed. At the same time, the voltage to be applied to the source terminal should be accurately controlled during both the programming and the reading step.
It has been common practice to connect the cell sources to ground during the programming and reading phases by using a predetermined number of pass transistors, usually of the n-channel type.
FIG. 3
shows an array sector
11
having four pass transistors
16
placed at each sector apex and individually driven by a SRCCON signal.
The reason for having a ground connection established through pass transistors is that the cell source terminals, to which a varying positive voltage can be applied during the erasing phase, should not be constantly left connected to ground. During the programming phase, the value of the source voltage undergoes modulation due to the parasitic resistances of the lines and the pass transistors through which the source is taken to ground, as do the voltages to the drain and body terminals of the memory cells. This results in the effectiveness of the pulses that vary with the number of cells to be programmed. In addition, the source voltage thus modulated has a drawback in that it affects the drain-source V
DS
and body-source V
BS
voltage drops, and especially the gate-source V
GS
voltage drop with attendant overdrive.
The effects of source voltage modulation also occur during the verifying and reading operations. The outcome of a modulated source voltage is illustrated by the graph of
FIG. 4
showing a sequence of voltage-current characteristics of a generic array cell. Characteristic (
1
) will be considered first. For the cells to be regarded as erased, they must have a larger current than the one of the reference EV (erase verify) as to their gates is applied a voltage V
READ
. Under this condition, a large current is injected through the source terminal S, resulting in the characteristic portion for the largest currents taking a bend. Since the condition to be verified is a current, it can only be met by keeping the cell threshold voltages slightly below those of the cell EV. Characteristic (
1
) is that of a generic cell, such as i-th cell.
As to characteristic (
2
), let us assume that the write buffer containing the i-th cell is to be programmed with a pattern where all the cells are at the distribution with less current (i.e. a “00” distribution, past the reference cell PV
3
), with the exception of the i-th cell which is programmed for the second distribution (“10” distribution, past the reference cell PV
1
). Since during the programming step the cells progress approximately at the same rate, characteristic (
2
) for the i-th cell can be taken to be similar to that of the other cells. Here again the characteristic shows a bend due to the injection through the source terminal still being quite high, although lower if compared to the first characteristic. The i-th cell is verified to have been programmed at the desired distribution, and is then disconnected from its program-load circuit, whereas the other cells keep receiving pulses until the desired threshold is reached.
As regards characteristic (
3
), all the cells have attained their desired distributions and are read. The injection through the source terminal will be quite moderate because the thresholds of all the cells but the i-th lie above the read voltage. Therefore, the characteristic of the i-th cell will no longer show a bend in the large-current range. Thus, if no additional margin has been considered for source voltage modulation, the sense amplifier may erroneously read (or verify) the i-th cell.
The above is just a simple qualitative example of how heavily the modulation of the source voltage may be felt, and of how the method of this invention can make this modulation a constant one for each cell, irrespective of the charge state of the other cells with which it is read or verified, especially if the target is a m
Micheloni Rino
Motta Ilaria
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Audong Gene N.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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