Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-02-21
1997-04-01
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular biasing
36518523, 36518526, 36518529, G11C 1602
Patent
active
056173563
ABSTRACT:
A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
REFERENCES:
patent: 5051953 (1991-09-01), Kitazawa et al.
IEEE Journal Of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, New York US, pp. 1600-1605, Nakayama et al. "A 60ns 16-Mb Flash EEPROM With Program and Erase Sequence Controller".
Golla Carla
Olivo Marco
Padoan Silvia
Clawson Jr. Joseph E.
Driscoll David M.
Morris James H.
SGS--Thomson Microelectronics S.r.l.
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