Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-09-09
2001-05-08
Hoang, Huan (Department: 2812)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S189110
Reexamination Certificate
active
06229732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to floating gate memory devices, and more particularly to circuits for generating a negative voltage to be applied to a control gate and a positive voltage to be applied to a source, a drain or a channel, in such a way that a constant electric field is maintained across the memory cell for inducing Fowler-Nordheim tunneling.
2. Description of Related Art
Flash memory devices are based on arrays of floating gate memory cells which are programmed in some cases by biasing the memory cells to induce hot electron injection into the floating gate increase the threshold of the memory cell. Also, in many examples the cells are erased by biasing the cells to induce Fowler-Nordheim tunneling of electrons out of the floating gate in order to establish a low threshold state. One common approach inducing Fowler-Nordheim tunneling for the erase operation is referred to as source side erase. According to this approach, a negative voltage is applied to the wordline of cells in the array to be erased, while a positive voltage or ground, is applied to the source. This biasing establishes an electric field between the floating gate and the source to induce Fowler-Nordheim tunneling. While the gate receives a negative voltage and the source receives a positive voltage or ground, the substrate is grounded and the drain is typically left floating. See U.S. Pat. No. 5,077,691; invented by Haddad, et al.; issued Dec. 31, 1991.
To support the source side erase operation, integrated circuits include a negative voltage charge pump or other source of negative voltage on the integrated circuit. In preferred systems, the voltage on the source side is as high as possible to reduce the magnitude of the negative voltage needed on the gate to establish sufficient electric field for tunneling. Also, it is known that a higher source voltage will induce higher band-to-band current on the source side and improve the efficiency of the tunneling. However, it is found that because of variations in the supply potential VDD of as much as 10% according to industry standards, and variations in current loading on the cells, the voltage applied to the source of a flash cell during source side erase cannot be maintained constant in many circumstances. As a result, the electric field across the floating gate and source will vary, and the erase time for cells can vary dramatically. There have been some attempts to regulate the negative voltage generation. See for example Venkatesh, et al., “A 55 ns 0.35 Micron 5V-Only 16 M Flash Memory With Deep-Power-Down” ISSCC 96/Session 2/Flash Memory/Paper TP2.7, pp. 44-45, 1996. However, it is desirable to provide an improved control over the erase time of flash memory cells, while maintaining the efficiency of the erasing operation.
SUMMARY OF THE INVENTION
According to the present invention, a circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to a complementary node comprising the source, the drain or the channel, which comprises a positive voltage source that is responsive to a supply voltage to provide a positive voltage to the source (in a preferred embodiment) of the cell and a negative voltage source responsive to the supply voltage providing a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the positive voltage. The positive voltage and the negative voltage establish an electric field between the floating gate and the source (or other complementary node) of the memory cell to be erased. The regulator maintains the negative voltage in response to the positive voltage so that the electric field remains essentially constant over a range of values of the positive voltage, or alternatively maintains an essentially constant erase speed.
The electric field established between the floating gate and the source (or other complementary node) can be modeled by a physical relationship. The regulator according to one aspect of the invention, comprises a circuit that has a transfer function modeling the physical relationship to compensate for variations in the electric field over a range of values of voltage.
According to one aspect of the invention, the regulator comprises an amplifier that has a first input coupled to the positive voltage, a second input coupled to a reference potential, and an output coupled to the negative voltage source. Feedback is connected between the output of the negative voltage source and the second input to induce the output of the negative voltage source to track changes in the source voltage.
In one preferred aspect, the regulator comprises a level shift circuit coupled to the negative voltage generator, including for example a zener diode. A voltage divider is coupled between the level shift circuit and a reference potential and supplies a feedback voltage indicating variations in the negative voltage supplied by the negative voltage generator. A n-channel MOS transistor has a drain coupled to the supply voltage, a gate coupled to the positive voltage, and a source. A p-channel MOS transistor has a source coupled to the source of the n-channel MOS transistor, a gate coupled to the feedback voltage from the voltage divider, and a drain coupled to the negative voltage generator, through for example a level shifting circuit.
According to another aspect of the invention, a clamp circuit is coupled to the source of the n-channel MOS transistor to prevent the source of the n-channel MOS transistor from dropping below a clamp level.
The present invention can also be characterized as an integrated circuit memory comprising an array of floating gate memory cells, and circuits for reading, programming and erasing the memory cells in the array. According to this aspect of the invention, the circuit for erasing the memory cells in the array includes resources to apply a negative voltage to wordlines in the array and a positive voltage across the conductive paths to sources (or other complementary nodes) of memory cells in the array, and to maintain an essentially constant electric field across the floating gates and sources of memory cells in the array over a range of source voltages. The constant electric field according to a preferred aspect of the invention is maintained utilizing the voltage regulating technique discussed above.
The present invention thus provides a method for erasing floating gate memory cell based on applying a positive voltage to the source (or other complementary nodes) and applying a negative voltage to the control gate. In addition, the method involves regulating the negative voltage to maintain the negative voltage at a level responsive to the positive voltage on the source. The level responsive to the source voltage is regulated so that the electric field remains essentially constant between the floating gate and the source of the cell over a range of values of the source voltage. The regulating according to another aspect of the invention, the source voltage and a negative voltage establish an electric field between the floating gate and the source of the memory cell to be erased according to a physical relationship. The regulating of the negative voltage is accomplished by a circuit having a transfer function modeling the physical relationship.
In this manner, integrated circuit memory device having a constant erase speed can be provided. With a constant erase speed, the control circuitry for erasing the array of cells, can be improved.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.
REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5282170 (1994-01-01), Van Buskirk et al.
patent: 5349220 (1994-09-01), Hong
patent: 5406524 (1995-04-01), Kawamura et al.
patent: 5581107 (1996-12-01), Kawamura et al.
patent: 561292
Lin Yu-Shen
Shiau Tzeng-Huei
Wan Ray-Lin
Haynes Mark A.
Haynes & Beffel LLP
Hoang Huan
Macronix International Co. Ltd.
LandOfFree
Regulated voltage supply circuit for inducing tunneling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Regulated voltage supply circuit for inducing tunneling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Regulated voltage supply circuit for inducing tunneling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2532623