Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-10-05
2003-01-07
Sterrett, Jeffrey (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S097000
Reexamination Certificate
active
06504735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to DC-DC electrical power oonverter circuits, and more specifically to DC-DC power converter circuits adapted for converting electrical energy received from a high-voltage, poorly regulated electrical power source to a well regulated lower voltage.
2. Description of the Prior Art
U.S. Pat. No. 5,999,417 entitled “High Efficiency Power Converter,” that issued Dec. 7, 1999, on a patent application filed by Martin F. Schlecht (“the '417 patent”), describes a DC-DC converter circuit adapted for converting electrical power received from a 48 volt direct current (“VDC”) power source to a 5 VDC output voltage for energizing the operation of computer digital logic circuits. As illustrated in FIG. 1 of the '417 patent, the DC-DC converter disclosed there includes a regulation stage, an isolation stage, and control circuit that is coupled both to the regulation stage and to the isolation stage.
FIG. 2 of the '417 patent depicts as the regulation stage a conventional voltage step-down converter circuit, a/k/a/ a buck converter circuit, which receives the 48 VDC battery voltage. Within the buck converter circuit, the 48 VDC battery voltage is applied across a capacitor, C
IN
, and from a first terminal of the 48 VDC battery to a switching transistor, Q
R
. When the switching transistor, Q
R
, turns-on, electrical current flows from the 48 VDC battery source through the switching transistor, Q
R
, and through a series connected inductor L into the isolation stage of the DC-DC converter. During normal operation of the buck converter circuit when the switching transistor, Q
R
, turns-off to block current from flowing from the 48 VDC battery source through the inductor L, electrical current continues to flow through the inductor L via a free-wheeling diode, D
R
, that connects between a second terminal of the 48 VDC battery source and a junction between the inductor L and the switching transistor, Q
R
.
A version of the isolation stage of the DC-DC converter, illustrated in FIG. 2 of the '417 patent, includes two, separate transformers T
1
and T
2
. Each of the transformers T
1
and T
2
includes three windings: a primary winding T
1
PRI
and T
2
PRI
; a secondary winding T
1
SEC
and T
2
SEC
; and a tertiary winding T
1
TER
and T
2
TER
. The primary windings T
1
PRI
and T
2
PRI
of the transformers T
1
and T
2
are coupled to the inductor L of the regulator stage to receive electrical current therefrom, and are coupled respectively through MOSFETs Q
1
and Q
2
to the second terminal of the 48 VDC battery source. Connected in this way, while either of the transistors Q
1
or Q
2
are turned-on, the primary windings T
1
PRI
and T
2
PRI
of the transformers T
1
and T
2
are “current fed” from the inductor L of the regulation stage. By this it is meant that the electrical current flowing into the primary windings T
1
PRI
and T
2
PRI
of the isolation stage transformers T
1
and T
2
is held relatively constant throughout a switching cycle of the DC-DC converter. It also means that voltage across the primary windings T
1
PRI
and T
2
PRI
of the isolation stage transformers T
1
and T
2
is free to have large, high frequency components.
During normal operation of the DC-DC converter, approximately one half of the switching cycle, transistor Q
1
is turned-on and transistor Q
2
is turned-off. While the transistor Q
1
is turned-on, electrical current flows through the series connected inductor L and primary winding T
1
PRI
of transformer T
1
. During a second half of the switching cycle, transistor Q
2
is turned-on, and transistor Q
1
is turned-off. While the transistor Q
2
is turned-on, electrical current flows through the inductor L and through the primary winding T
2
PRI
of the transformer T
2
in the same manner as described above for transformer T
1
,
While the transistor Q
1
is turned-on, a positive voltage is imposed across the primary winding T
1
PRI
, and a magnetizing current flowing through the primary winding T
1
PRI
increases. The voltage applied across the primary winding T
1
PRI
and the current flowing therethrough induce a corresponding flow of electrical current (transformed by the turns ratio between the primary winding T
1
PRI
and the secondary winding T
1
SEC
) through the secondary winding T
1
SEC
of the transformer T
1
, and through a diode D
1
connected in series with the secondary winding T
1
SEC
both to an output filter capacitor C
OUT
and to a load that is coupled to the isolation stage. When the transistor Q
1
turns-off thereby blocking an electrical current from flowing through the primary winding T
1
PRI
, the voltages across the windings T
1
PRI
, T
1
SEC
and T
1
TER
reverse thereby causing electrical current to flow through the tertiary winding T
1
TER
of the transformer T
1
and a diode D
3
connected in series with the tertiary winding T
1
TER
to the output filter capacitor C
OUT
and the load. Electrical current flowing through the tertiary winding T
1
TER
of the transformer T
1
provides a means to reset the core of the transformer T
1
, and to recover most of the magnetizing inductance energy stored in the core while the transistor Q
1
is turned-on. Since as described above the transistors Q
1
and Q
2
operate out of phase, the transformer T
2
operates similar to but out of phase with the transformer T
1
for supplying electrical currents respectively through the secondary winding T
2
SEC
and a diode D
2
, and the tertiary winding T
2
TER
and a diode D
4
to the output filter capacitor C
OUT
and the load.
The control circuit illustrated in FIG. 1 of the '417 patent provides drive signals to control terminals of the transistors Q
R
, Q
1
and Q
2
illustrated in FIG. 2. The '417 patent explains that the separate regulation stage, which in the illustration of FIG. 1 is on the primary side of the converter's isolation stage, regulates operation of the DC-DC converter. In this particular configuration, regulation is effected by controlling the duty cycle of the transistor Q
R
in response to one or more parameters sensed in the control circuit, which may be sensed on the primary side of the converter's isolation stage.
A significant fraction of the energy dissipated in a DC-DC converter such as that depicted in FIG. 2 of the '417 patent occurs in the diodes D
1
, D
2
, D
3
and D
4
, particularly if the load and/or source voltages are low, e.g. 3.3, 5, or 12 volts. To reduce this rectification conduction power loss, the diodes D
1
, D
2
, D
3
and D
4
may be replaced with transistors which have an on-state voltage that is much less than the conduction voltage drop of the diodes D
1
, D
2
, D
3
and D
4
. Transistors used in this way are frequently called synchronous rectifiers, and are typically power MOSFETs for DC-DC converters switching in the 100 kHz and higher range.
FIGS. 3, 5, 6A, 6B and 7-9 of the '417 patent illustrates an isolation stage for the DC-DC converter in which a pair of N-channel MOSFET synchronous rectifiers Q
3
and Q
4
replace the diodes D
1
, D
2
, D
3
and D
4
. The positions of these synchronous rectifiers Q
3
and Q
4
in the circuit differs slightly from the positions of the diodes D
1
, D
2
, D
3
and D
4
in FIG. 2. The synchronous rectifiers Q
3
and Q
4
still connect in series with the respective secondary winding T
1
SEC
and T
2
SEC
, but drains of the N-channel MOSFET synchronous rectifiers Q
3
and Q
4
connect to the negative output terminal of the respective secondary windings T
1
SEC
and T
2
SEC
rather than to the positive output terminal. The synchronous rectifiers Q
3
and Q
4
connect in this way to the respective secondary winding T
1
SEC
and T
2
SEC
so source terminals of both N-channel MOSFET synchronous rectifiers Q
3
and Q
4
connect to a single, common DC node, i.e. circuit ground.
If instead of N-channel MOSFETS, P-channel MOSFETs were used for the synchronous rectifiers Q
3
and Q
4
, their respective drain terminals would connect to
Negru Sorin Laurentiu
Nicolescu Gabriel Andreis
02 Micro International Ltd.
Schreiber D. E.
Sterrett Jeffrey
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