Register stage having at least two memory stages for coordinatin

Details Register stage having at least two memory stages for coordinatin Register stage having at least two memory stages for coordinatin

1994-06-02

1996-02-13

Voeltz, Emanuel T.

Excavating

371 223, 371 225, G01R 313185

Patent

active

054916992

ABSTRACT:
For testing an integrated circuit with sequential logic its register stages are arranged in series as a shift register. This may give rise to delay time problems, which can be avoided by two-phase operation of the register stages, as is the case in, for example, the known LSSD technology. However, for a high processing speed edge-clocked register stages are more favorable. The invention therefore proposes register stages which can readily be switched between two-phase operation during testing and edge control in normal operation. For this only one additional clock line is required.

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