Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Low workfunction layer for electron emission
Reexamination Certificate
2002-02-22
2004-03-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Low workfunction layer for electron emission
C710S120000, C710S120000, C710S306000, C711S001000, C711S002000, C711S202000, C365S222000, C365S236000
Reexamination Certificate
active
06713778
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a register setting method, and more particularly, to a method of setting a resistor for storing data for controlling a variety of operational specifications of a device, and a semiconductor device.
A semiconductor device typically has a large number of operation modes so that an optimal operation mode for a user's system is set in the semiconductor device. The semiconductor device comprises a mode register for storing an operation mode setting value. The semiconductor device operates based on the operation mode setting value stored in the mode register.
The mode register setting value is generally supplied from an external device in response to a mode register set (MRS) command. The MRS command is a command for initially setting the operation mode of the semiconductor device. The MRS command is supplied from a system in response to a power-on of the system or a released reset signal associated with a system reset. More specifically, in accordance with the MRS command, the mode register in the semiconductor device stores set values for operation conditions (hereinafter called the “operation condition information”), for example, a CAS latency (2 clocks, 3 clocks, or 4 clocks), an addressing mode (sequential mode or interleave mode), burst (burst length: 0, 2, 4, or 8), and the like.
FIG. 1
is a schematic block circuit diagram of a semiconductor device
100
according to a first prior art example.
The semiconductor device
100
is, for example, an EEPROM or a flash memory, i.e. a non-volatile semiconductor memory device. A mode register
11
stores a previously set initial value for the operation condition information (hereinafter called the “default value”) as the semiconductor device
100
is powered on. The default value is set by a ROM which stores information, for example, by cutting a predetermined element with a laser, or by a latch circuit which is set to have a constant value by a power supply. The mode register
11
, in response to a start signal stt, supplies a memory control circuit
12
with a control signal including the stored default value. The memory control circuit
12
, in response to the control signal, controls peripheral circuits (for example, an input/output circuit). The semiconductor device
100
operates in accordance with the default value.
A MRS control circuit
13
generates a set signal in response to a MRS command, and supplies the set signal to the mode register
11
. The MRS command is specified by a combination of levels of a plurality of control signals. Specifically, when a command generated by decoding a plurality of control signals is an MRS command, the MRS control circuit
13
supplies the mode register
11
with a set signal based on an address (ADD) signal. The mode register
11
stores a variety of set values in response to the set signal, and generates a memory control signal in accordance with the set values, and supplies a memory control signal to the memory control circuit
12
. In this event, the semiconductor device
100
operates in accordance with newly set operation condition information.
FIG. 2
is a diagram illustrating a sequence of operations in the first prior art example including the user's system.
As the device
100
is powered on, a start signal stt is generated within the device
100
(step S
1
), and the mode register
11
is set to a default value (step S
2
). At this time, information in the mode register
11
is established (step S
3
).
Next, it is determined whether or not an operation condition (mode) has been changed (step S
4
). When the operation condition is not changed, the mode register
11
supplies a memory control signal to the memory control circuit
12
(step S
5
). In response to the memory control signal, the memory control circuit
12
operates, causing the device
100
to perform an operation such as read/write.
Afterwards, the mode register
11
is rewritten by an MRS command for adapting the operational specifications of the device to system's operational specifications on the user side. When the operation condition is changed, a mode control signal is generated (step S
6
), and the MRS control circuit
13
decodes a command to generate a register set signal which is supplied to the mode register
11
(step S
7
). Thus, new operation condition information is set in the mode register
11
(step S
3
).
The mode register
11
is a memory having a fast write and read operation so that its setting can be immediately changed, and is typically implemented by a volatile memory. Therefore, a set value must be written into the mode register
11
by an external device each time a system, equipped with the semiconductor device
100
including the mode register
11
, is powered on or reset. The rewriting results in a longer start-up time from power supply to the device to the actual operation of the device adapted to new specifications.
FIG. 3
is a schematic block circuit diagram of a semiconductor device
200
according to a second prior art example.
The semiconductor device
200
includes a load register
22
for transferring a set value (operation condition information) to a mode register
21
. The load register
22
has a rewrite control circuit
22
a
and a non-volatile RAM
22
b
. The control circuit
22
a
receives a rewrite command (LRW command: Load Register Write command) from an external device. The control circuit
22
a
rewrites the contents of the non-volatile RAM
22
b
in response to the LRW command.
The load register
22
, in response to a start signal stt, transfers the set value stored in the non-volatile RAM
22
b
to the mode register
21
. The mode register
21
generates a memory control signal in accordance with the set value, and supplies the memory control signal to a memory control circuit
23
.
Since the semiconductor device
200
includes the non-volatile RAM
22
b
of the load register
22
, the set value does not need to be set again in the mode register
21
each time the system is powered on or the system is reset.
FIG. 4
is a diagram illustrating a sequence of operations in the second prior art example.
As the device
200
is powered on, a start signal stt is generated within the device
200
(step S
11
), and an initial value is set in the load register
22
in response to the start signal stt (step S
12
). The load register
22
loads the initial value into the mode register
21
(step S
13
) to establish initial information in the mode register
21
(step S
14
).
Next, it is determined whether or not the operation condition (mode) has been changed (step S
15
). When the mode is not changed, the mode register
21
supplies a memory control signal to the memory control circuit
23
(step S
16
). The memory control circuit
23
operates in response to the memory control signal, causing the device to perform an operation such as read/write.
Afterwards, the mode register
21
is rewritten by an MRS command for adapting the operational specifications of the device to the system's operational specifications of the user. When the mode is changed, a mode control signal is generated (step S
17
). An MRS control circuit
24
decodes a command to generate a register set signal which is supplied to the mode register
21
(step S
18
). At this time, new operation condition information is set in the mode register
21
(step S
14
).
As the device
200
is once shut off, the set value (initial value) of the mode register
21
, after the device
200
is again powered on is loaded again from the load register
22
and stored in the mode register
21
.
When the content of the load register
22
is changed, the system generates a rewrite command (LRW command) (step S
19
). The rewrite control circuit
22
a
supplies rewrite information to the non-volatile RAM
22
b
in response to the LRW command (step S
20
) to rewrite the contents of the non-volatile RAM
22
b
. Therefore, when the device
200
is powered on at a later time, a new initial value is loaded into the mode register
21
. The memory control circui
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Tran Mai-Huong
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