Register robustness improvement circuit and method

Details Register robustness improvement circuit and method Register robustness improvement circuit and method

1987-12-09

1990-09-25

Atkinson, Charles E.

Excavating

G06F 1108

Patent

active

049598368

ABSTRACT:
The present invention describes a robust register circuit for protecting critical control points in data transmission and telecommunications equipment against software included failures. A circuit is provided wherein duplicated data words are written into a pair of registers of any desired bit length. A digital comparator determines whether the two data words are the same, and initiates a data transfer into a third register for transmission to critical hardware control points only when two identical sequential data words are recognized. When no such recognition occurs, new data is not transferred to the third register, and the hardware control points remain controlled by the previous data in the third register.

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Research Disclosure 26134, Jan. 1986, "Buffer Memory with Detection of Data Errors and Errors Caused by Faults in the Read and Write Address Registers".

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