Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-06-05
2001-02-13
Gordon, Paul P. (Department: 2786)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S097000, C700S098000, C700S108000, C700S109000, C700S121000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06188934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a register correspondence method in a logic equivalence verifying system.
2. Description of the Related Art
As verifying functions of circuits, use is generally made of simulation methods. Particularly, if the function of a circuit is written in hardware description language (HDL), a designer recognizes the function of circuit by a simulation method. Then, the designer designs a new circuit by modifying the HDL written circuit using a logic synthesis system or manually. In this case, the designer again verifies the function of the new circuit by a simulation method with reference to the result of the above-mentioned simulation method.
In the above-mentioned verifying method using simulation methods, however, if the circuit becomes remarkably large, it takes a long time to verify the circuit since a large number of test patterns are required.
In order to reduce the verifying time, a prior art logic equivalence verifying system for directly comparing circuit information with reference circuit information has been developed (see JP-A-8-22485).
In this logic equivalence verifying system, a circuit analysis section analyzes two kinds of circuit information to recognize external terminals, registers and combination circuits from each of the circuit information. Next, a register correspondence section makes a register correspondence between two kinds of the circuit information automatically or manually. Next, a logic extraction section extracts logic information of the combination circuits of the two kinds of circuit information as a binary decision diagram (BDD) for every verification point. This will be explained later in detail.
However, if the register correspondence section of the prior logic equivalence verifying system is forcibly applied to a sequential circuit having a feedback loop, the register correspondence processing time is increased.
Further, in the prior art register correspondence, if test circuits are added in circuit information, it is impossible to make a register correspondence.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a register correspondence method in a logic equivalence verifying system which can be carried out even when circuit information includes a feedback loop and test circuits.
According to the present invention, in a register correspondence method in a logic equivalence verifying system for first and second sequential circuit information, input cone information is collected for each register of the first and second sequential circuit information. The input cone information is represented by external input terminals, determined registers, a number of undetermined registers and self-feedback information showing presence or absence of a self-feedback loop. Then, a first register having unique input cone information is selected from the first sequential circuit information, and a second register having unique input cone information is selected from the second sequential circuit information. Then, the input cone information of the first register is compared with the second register, thus establishing a register correspondence between the first and second registers.
Also, before the input cone information is collected, constant signals to circuit elements of the first and second sequential circuit information are propagated and connections to input terminals of the circuit elements are cut.
REFERENCES:
patent: 5497499 (1996-03-01), Grag et al.
patent: 5671395 (1997-09-01), Akiyama
patent: 5831996 (1998-11-01), Abramovici et al.
patent: 5903467 (1999-05-01), Puri et al.
patent: 5907698 (1999-05-01), Kucukcakar et al.
patent: 5933349 (1999-08-01), Dalgleish et al.
patent: 5949691 (1999-09-01), Kurosaka et al.
patent: 5966521 (1999-10-01), Takeuchi et al.
patent: 6000038 (1999-12-01), Scepanovic et al.
patent: 6006023 (1999-12-01), Higashida
patent: 6026219 (2000-02-01), Miller et al.
patent: 6032082 (2000-02-01), Anazawa
patent: 6-20000 (1994-01-01), None
patent: 8-22485 (1996-01-01), None
Foley & Lardner
Gordon Paul P.
NEC Corporation
Patel Ramesh
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