Register bus multiprocessor system with shift

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364DIG1, 3642293, 3642595, 370 851, 370 8515, G06F 1300, G06F 1516

Patent

active

051194813

ABSTRACT:
A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

REFERENCES:
patent: 3748647 (1973-07-01), Ashany et al.
patent: 4011545 (1977-03-01), Nadiv
patent: 4031512 (1977-06-01), Faber
patent: 4334305 (1982-06-01), Girardi

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