Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Patent
1997-06-30
1999-12-28
Hafiz, Tariq R.
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
395707, 395708, 712217, G06F 945
Patent
active
060092726
ABSTRACT:
An approach for allocating a set of virtual registers to a set of physical registers using selective spilling is described. A set of code and a spill variable are specified. A code region hierarchy containing a set of code regions is determined based upon the set of code. The first level of the code region hierarchy is evaluated and if the spill variable is referenced in more than one code region, code for performing a spill operation on the specified spill variable is added to the set of code based upon a code region which defines the specified spill variable. In addition, code for performing a reload operation on the specified spill variable is added to the set of code based upon code regions that use the specified spill variable. If the spill variable is only referenced in a single code region in the first level of the code region hierarchy, then code regions that are both in a second level of the code region hierarchy and which correspond to the code region in the first level which references the spill variable are analyzed and code added in a similar manner.
REFERENCES:
patent: 4571678 (1986-02-01), Chaitin
patent: 4763255 (1988-08-01), Hopkins et al.
patent: 4782444 (1988-11-01), Munshi et al.
patent: 5233691 (1993-08-01), Ando et al.
patent: 5249295 (1993-09-01), Briggs et al.
patent: 5418958 (1995-05-01), Goebel
patent: 5481706 (1996-01-01), Peek
patent: 5530866 (1996-06-01), Koblenz et al.
patent: 5590329 (1996-12-01), Goodnow, II et al.
patent: 5659754 (1997-08-01), Grove et al.
patent: 5761514 (1998-06-01), Aizikowitz et al.
patent: 5774730 (1998-06-01), Aizikowitz et al.
patent: 5778233 (1998-07-01), Besaw et al.
Fred C. Chow et al., "The Priority-Based Coloring Approach to Register Allocation", 10872 ACM Transactions on Programming Languages and Systems, vol. 12, No. 4, Oct. 1990, pp. 501-536.
Gregory J. Chaitin et al., "Register Allocation Via Coloring", 10871 Computer Languages, vol. 6, 1981, pp. 47-57.
Weaver, David L. et al., "The SPARC Architecture Manual" Prentice Hall, Version 9, (1991) pp. 294-298.
Aho, Alfred V. et al., "Intermediate Code Generation", Compilers Principles, Techniques and Tools, Chapter 8, Addison-Wesley, (1988), pp. 463-512.
Kolson et al., "Optimal Register Assignment to Loops for Embedded Code Generation", Association for Computing Machinery, 1995, pp. 42-47.
Callahan et al., "Register Allocation via Interference Graph Coloring", Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 1991, pp. 192-203.
Chaki Kakali
Hafiz Tariq R.
Sun Microsystems Inc.
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