Register allocation technique

Details Register allocation technique Register allocation technique

2007-12-25

2007-12-25

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S216000

Reexamination Certificate

active

11155755

ABSTRACT:
A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations (“uops”).

REFERENCES:
Collins et al., “Clustered Multithreaded Architectures—Pursuing both IPC and Cycle Time”, Proceedings of the 18thAnnual Parallel and Distributed Processing Symposium, IEEE, Apr. 26-30, 2004, 10 pages.
Canal et al., “Dynamic Code Partitioning for Clustered Architectures”, International Journal of Parellel Programming, Springer Netherlands, vol. 29, No. 1, Feb. 2001, pp. 59-79.
Canal et al., “Dynamic Cluster Assignment Mechanisms”, Proceedings of the 6thInternational Symposium on High Performance Computer Architecture, IEEE, Jan. 8-12, 2000, 10 pages.

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