Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1977-12-02
1979-01-16
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307216, 307264, 307DIG3, 364862, 365183, 365222, 357 24, H01L 2710, H01L 2978, H03K 1908, H03K 518
Patent
active
041351045
ABSTRACT:
The problem of gradual dissipation of charge in charge packets in charge-coupled devices (CCDs) as the packets are successively shifted is overcome by a regenerator circuit which also provides a basic structure for effecting elemental logic and arithmetic functions. A standardized charge packet is injected along with a digitally valued but somewhat diminished charge packet into a potential well under a storage electrode arranged to retain a single charge packet. Overflow from the storage electrode region that represents only some part of a full charge packet is detected by a master sensing gate that controls a slave gate forming a shunt path for the full charge packet and that is normally maintained in a transfer state. The slave gate shifts to a barrier state when the overflow packet is present, however, permitting the full charge packet to advance along another electrode path. Consequently, when a diminished charge packet having an assigned binary value is applied to the regenerator circuit, a full charge packet representing the same binary value is transferred out, and without inversion. In the absence of a charge packet at the binary input indicating the alternate binary value, the unitary charge under the storage electrode is directed out the shunt path. Advantageous arrangements are provided for in-line transfer of the data signal, sequential advance of the charge packets and dissipation of charge residues. By appropriate use of additional input transfer gates and output transfer gates, the regenerator circuit serves as a basic unit which can provide fundamental logical and digital functions needed in digital systems, including OR gates, AND gates, EXCLUSIVE-OR gates, half adders and full adders.
REFERENCES:
patent: 3777186 (1973-12-01), Chang
patent: 3919564 (1975-11-01), Walden
patent: 3937985 (1976-02-01), Cooper, Jr.
patent: 3986059 (1976-10-01), Mohsen
patent: 3989956 (1976-11-01), Walden
patent: 4047051 (1977-09-01), Heller
patent: 4048519 (1977-09-01), Hoffmann et al.
patent: 4082963 (1978-04-01), Hoffman
Chou, "Design of a 16384-Bit Serial Charge-Coupled Memory Device"; IEEE Trans. on Electron Devices, vol. ED-23, No. 2, pp. 78-86; Feb. 1976.
Dennard, "Regeneration Circuit for Charge-Coupled Device Shift Register", IBM Tech. Discl. Bull.; vol. 14, No. 12, pp. 3791-3792; May 1972.
Anantha, "Charge Sensing Circuit Using Charge Amplification"; IBM Tech. Discl. Bull.; vol. 18, No. 12, pp. 4019-4020; May 1976.
Anagnos Larry N.
TRW Inc.
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