Regenerative strobe circuit for CMOS programmable logic array

Details Regenerative strobe circuit for CMOS programmable logic array Regenerative strobe circuit for CMOS programmable logic array

1985-12-23

1987-09-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307481, 307577, 307579, G11C 8000, H03K 1716, H03K 19096, H03K 17687

Patent

active

046926399

ABSTRACT:
A regenerative strobe circuit for a CMOS logic gate which only dissipates energy during the strobing of the inputs into the logic array is provided. The logic gate is connected between an output node and a first voltage source. The regenerative strobe circuit includes a first transistor (P channel) which is connected between a second voltage source and the output node, a complementary inverter having P channel transistor and N channel transistor, and second and third transistors which are respectively gate controlled by a strobe signal and a signal related to the strobe signal. The second transistor (P channel) is also connected between the second voltage source and the source of the P channel transistor of the complementary inverter. The third transistor (preferably P channel) is connected to the gate of the first transistor as well as to the source of the N channel transistor of the complementary inverter. The source of the N channel transistor of the complementary inverter is connected to said first voltage source. The gate of the first transistor is also connected to the common drains of the transistors of the complementary inverter.

REFERENCES:
patent: 3479523 (1969-11-01), Pleshko
patent: 3911289 (1975-10-01), Takemoto
patent: 3988617 (1976-10-01), Price

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