Refresh techniques for memory data retention

Details Refresh techniques for memory data retention Refresh techniques for memory data retention

2003-04-25

2004-06-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185250

Reexamination Certificate

active

06754101

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory arrays, and more particularly relates to data retention in such memory arrays.
A data retention problem exists in a non-volatile memory array (such as flash, EEPROM etc.) during power-on state. After a cell is programmed or erased, several mechanisms disturb the charge stored on the floating gate. Some of these processes are listed below:
(a) Oxide leakage—oxide leakage occurs even when the power is off and is a function of the amount of charge stored on the floating gate as well as the physical oxide characteristics (such as thickness and structure quality). Oxide leakage is unavoidable and is best addressed by fabrication process techniques.
(b) Read disturb—When power is on and a cell is read from, a current passes through the access transistor. During current flow, energetic electrons and/or holes are generated which can tunnel into the floating gate disturbing the stored data. (When power is off, there is no reading of the cell, and no degradation of the stored data due to reading.)
(c) Neighbor disturb—During erase, program or read operations the neighboring cells which share the word lines, program lines and bit lines with the cell being accessed are also affected through these shared lines. By design, this disturbance is minimized but is not completely eliminated.
(d) Supply noise—When the supply voltages are on, a noise event due to coupling or other current spikes can cause an unexpected voltage drop resulting in data disturbance.
The above noise events one at a time by themselves may not result in data corruption. However, after a long period of continuous operation, failure could result due to the integration of these (small) disturbance events.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
One apparatus embodiment of the invention is useful in a digital memory system including a memory cell arranged to store charge corresponding to first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored charges lies within a second range of values. In such an environment, the integrity of the data represented by the charge may be tested by apparatus comprising a bit line coupled to the cell and arranged to conduct charge on the bit line in response the charge stored in the cell and a charge integrity estimating module. The module is operative during a first mode of operation to detect whether the quantity of the charge lies within the first range of values or the second range of values, and is operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values. The module also is operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.
One method embodiment of the invention is useful in a digital memory system including a memory cell arranged to store charge corresponding to first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored charges lies within a second range of values and also including a bit line coupled to the cell. In such an environment, the integrity of the data represented by the charge may be tested by a method comprising detecting during a first mode of operation whether the quantity of the charge lies within the first range of values or the second range of values and detecting during a second mode of operation whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values. In addition, the method comprises detecting during a third mode of operation whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.
By using the foregoing techniques, a data can be retained in a memory array with a degree of accuracy previously unattained.
These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.


REFERENCES:
patent: 5157629 (1992-10-01), Sato et al.
patent: 5319253 (1994-06-01), You
patent: 5748544 (1998-05-01), Hashimoto
patent: 6147916 (2000-11-01), Ogura
patent: 6459635 (2002-10-01), Mullarkey et al.

Affiliated with

Also associated with

Rating

Refresh techniques for memory data retention does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Refresh techniques for memory data retention, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Refresh techniques for memory data retention will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3365843