Refresh operation control circuit for semiconductor device

Details Refresh operation control circuit for semiconductor device Refresh operation control circuit for semiconductor device

1987-02-06

1988-07-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307481, 307518, 307269, 3072721, 365222, H03K 3356

Patent

active

047572175

ABSTRACT:
This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

REFERENCES:
patent: 4403192 (1983-09-01), Williman
patent: 4406013 (1983-09-01), Reese et al.
patent: 4420695 (1983-12-01), Fisher
patent: 4578782 (1986-03-01), Kraft et al.
patent: 4620118 (1986-10-01), Barber
patent: 4622668 (1986-11-01), Dancker et al.
patent: 4625301 (1986-11-01), Berger
patent: 4677592 (1987-06-01), Sakurai et al.
Japanese Patent Publication (Kokoku) No. 55-49341; Hirotani et al., Jul. 23, 1974.
Japanese Patent Publication Nos. 61-5495 and 61-42794.

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