Refresh circuit for dynamic memory of a data processor employing

Details Refresh circuit for dynamic memory of a data processor employing Refresh circuit for dynamic memory of a data processor employing

1981-08-12

1985-12-03

Shaw, Gareth D.

Boots, shoes, and leggings

365222, G06F 1300

Patent

active

045569525

ABSTRACT:
In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.

REFERENCES:
patent: 4137565 (1979-01-01), Mager et al.
patent: 4158883 (1979-06-01), Kadono et al.
patent: 4218753 (1980-08-01), Hendrie
patent: 4317169 (1982-02-01), Panepinto et al.
"Memory Systems Design and Applications" Hayden Book Company, McCormick, pp. 181-184.

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