Reframe circuit in a synchronous multiplexing device

Details Reframe circuit in a synchronous multiplexing device Reframe circuit in a synchronous multiplexing device

1989-12-11

1991-05-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701001, 375116, H04J 306

Patent

active

050181408

ABSTRACT:
A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.

REFERENCES:
patent: 3903371 (1975-09-01), Colton et al.
patent: 3940563 (1976-02-01), Susset
patent: 4016368 (1977-04-01), Apple, Jr.
patent: 4404675 (1983-09-01), Karchevski
patent: 4747116 (1988-05-01), Yajima et al.
patent: 4748623 (1988-05-01), Fujimoto

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