Refractory metal capped low resistivity metal conductor...

Details Refractory metal capped low resistivity metal conductor... Refractory metal capped low resistivity metal conductor...

1998-07-10

2001-11-27

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S762000, C257S751000, C257S753000, C257S764000

Reexamination Certificate

active

06323554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacture of electrical conductor lines and vias that interconnect circuits on substrates such as semiconductors and related packages and, more particularly, to a low cost method of filling seams or holes in substrates using a combination of a low resistivity metal deposited by physical vapor deposition (PVD) and a refractory metal deposited by chemical vapor deposition (CVD). The invention has particular application in submicron circuit manufacture.
2. Description of the Prior Art
Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metals include Al
x
Cu
y
, where the sum of x and y is equal to one and both x and y are greater than or equal to zero and less than or equal to one, ternary alloys such as Al—Pd—Cu and Al—Pd—Nb, Al—Cu—Si, and other similar low resistivity metal based alloys. Today's emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacture has led to reliability problems including inadequate isolation, electromigration, and planarization.
The IBM Technical Disclosure Bulletin to Ahn et al., Vol. 33, No. 5, Oct. 1990, pages 217-218, discloses tungsten wrapped copper conductors and via holes fabricated by selective deposition using a mixture of WF
6
and SiH
4
in the presence of hydrogen. Encapsulated interconnects like those of Ahn et al. have significantly higher resistance to electromigration and the small grain size of a selective tungsten film reduces reflectance and thereby enhances the ability of photolithography tools to focus and resolve photoresist images. However, the tungsten layer formed using the low temperatures described by Ahn et al. would be silicon rich (e.g., 3-4%) and would not be a good diffusion barrier for copper since copper resistivity would be degraded by the formation of copper silicide. Thus, it is difficult to deposit a diffusion barrier by selective means at low temperature. Moreover, the Ahn et al. technique relies on the formation of a donut shape at the bottom of the lines which is normally created by the reaction of outgassing moisture and WF
6
. The creation of the donut shape is believed to be not reliable.
Dalton et al.,
VMIC Conference,
Jun. 12-13, 1990, pages 289-292, points out that a hot wall CVD reaction involving SiH
4
and H
2
reduction of WF
6
to form a selective tungsten layer on an aluminum or alloy conductor results in the incorporation of fluorine at the aluminum and tungsten interface. The fluorine incorporation is a byproduct of the reaction of WF
6
with aluminum as shown by Equation 1.
WF
6
+2Al→2AlF
3
+W   Eq. 1
The thin layer of aluminum fluoride will increase the series contact resistance of Metal 1 to Metal 2 vias. Dalton reported that sputtering TiW film on top of the aluminum prior to tungsten encapsulation using CVD eliminates the problem of fluorine absorption.
Dalton discloses a traditional scheme for interconnect formation wherein aluminum is first deposited on a planar surface, it is overcoated with the sputtered TiW layer (the only difference from traditional processing), the aluminum is then patterned using photoresist imaging and developing followed by reactive ion etching (RIE). The resulting structure is then overcoated with a passivation dielectric such as SiO
2
or polyimide which itself is subsequently patterned, subjected to RIE, and metallized to create a multilayered structure.
FIG. 1
is taken from Dalton and shows that multilayer devices produced by traditional processing schemes have seams in the dielectric layers at the location of the metal conductor lines and have a very irregular top surface.
It is difficult to achieve planarity of the dielectric using RIE. Planarity is in part dependent on the pattern density, and non-planar surfaces result in puddling problems during subsequent metalization. If an RIE technique is used on polyimide, an etch stop is needed for removal of photoresist on top of aluminum or copper based lines when the lines are etched down to the polyimide surface because the photoresist removal process would also remove polyimide. RIE of any high copper content, aluminum or copper alloy is extremely difficult. A serious drawback of traditional processes which include metal RIE is that a large number of metal shorts tend to develop with fine geometry due to particle defects.
U.S. Pat. No. 4,824,802 to Brown et al. discloses a method for filling interlevel dielectric vias or contact holes in multilevel VLSI metalization structures. In particular, an intermediary metal such as tungsten or molybdenum is either selectively deposited in openings in an insulator or non-selectively deposited over the entire surface and in the openings of the insulator by CVD, then a planarization resist, such as azoquinonenovolac-type resists, polymethacrylates, polyimides, or other thermoplastic materials, is applied over the top of the intermediary metal. A planarized structure is then obtained by etching to a level where the intermediary metal is even with the resist. The Brown et al. method does not avoid metal corrosion and other problems associated with etching and is not useful for planarizing Al—Cu or other soft alloys because they have different properties from the harder metals such as tungsten and molybdenum. Moreover, using the Brown et al. method, it is difficult to completely fill vias and lines.
U.S. Pat. No. 4,944,836 to Beyer et al. discloses a chemical-mechanical polishing technique which can be used to produce coplanar metal/insulator films on a substrate. In particular, Beyer et al. contemplate patterning an underlying insulating layer, depositing an Al—Cu film, and then using a chemical-mechanical polishing technique wherein an alumina slurry in dilute nitric acid is mechanically rubbed on the surface to remove Al—Cu. The polishing compound tends to have a significantly higher removal rate for Al—Cu than the underlying insulator. The resulting structure includes Al—Cu lines planarized with the insulating layer, and subsequent layers can easily be added in the fabrication of multilayer structures.
U.S. Pat. No. 4,956,313 to Cote et al. discloses a via filling and planarization technique wherein Al—Cu alloy lines are patterned on top of a first passivation layer on a substrate, the lines are overcoated with a second passivation layer which is preferably a doped glass such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) which conforms over the contours of the Al—Cu alloy lines, vias are then formed in the second passivation layer to expose the lines, and tungsten is applied over the surface of the second passivation layer and in the vias by CVD. It is reported in Cote et al. that CVD tungsten is conformal in character and can fill the vias without creating voids. The structure is then planarized by polishing with an abrasive slurry.
Neither Beyer et al. nor Cote et al. recognize that polishing is not practical for low resistivity, soft metals such as Al—Cu alloys. This is because such materials tend to scratch, smear on the surface, and corrode under the influence of the slurry. Moreover, creation of the planarized structures in accordance with Cote et al. takes several processing steps which increases costs and reduces output.
Rossnagel et al.
J. Vac. Sci. Technol.
2:261 (Mar/Apr. 1991) discloses a collimated magnetron sputter deposition technique for depositing films that are compatible with lift-off patterning techniques and hole filling. The technique is also presented in U.S. Pat. No. 4,824,544 which is herein incorporated by reference.
Shiozaki et al.,
Abstracts of the
19
th Conference on Solid State Devices and Materials
, discloses the use of selective tungsten deposition for hole filling on top of a high resistivity hard metal such as MoSi
x
and is unrelated to encapsulation of a soft metal.
SUMMA

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