Referencing scheme for trap memory

Details Referencing scheme for trap memory Referencing scheme for trap memory

2006-08-07

2008-11-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S210100

Reexamination Certificate

active

07447077

ABSTRACT:
A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

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