Referenceless ECL logic circuit

Details Referenceless ECL logic circuit Referenceless ECL logic circuit

1989-04-28

1990-05-22

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307454, 307494, 307354, H03K 19013, H03K 19086

Patent

active

049280244

ABSTRACT:
An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

REFERENCES:
patent: 4157509 (1979-06-01), Zielinski
patent: 4506171 (1985-03-01), Evans et al.
patent: 4626709 (1986-12-01), Mazumder et al.
patent: 4687953 (1987-08-01), Varadarajan
patent: 4714841 (1987-12-01), Shoji et al.
patent: 4719371 (1988-01-01), Fujita et al.
patent: 4745582 (1988-05-01), Fukushi et al.
patent: 4757474 (1988-07-01), Fukushi et al.

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