Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including passive device
Reexamination Certificate
2001-06-13
2003-01-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including passive device
C438S329000
Reexamination Certificate
active
06511889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates a reference voltage supply circuit which is used as a power supply circuit for an integrated circuit or such and particularly, to a reference voltage supply circuit, dispersion of whose reference output voltage caused by a fabrication process or such is suppressed.
2. Description of the Prior Art
When a reference voltage supply circuit is provided in a semiconductor device, a reference voltage supply circuit has in many cases been fabricated by a bipolar process, which is widely used for fabrication of an analogue circuit since there is a necessity of increasing relative precision of elements and precision in absolute value of a resistor. The reason why is also that since it is an analogue circuit that requires a reference voltage supply circuit, there is no other choice but to employ a bipolar process.
In recent years, an analogue circuit has been built even in a CMOS process which is used for a digital circuit in company with progress in integration of circuitry. Hence, there arises a necessity for a reference voltage supply circuit to be incorporated in a CMOS process.
FIG. 1
is a circuit diagram showing a conventional reference voltage supply circuit. The reference voltage supply circuit comprises two PNP transistors Q
31
and Q
32
whose collectors and bases are grounded. Resistor elements RE
33
and RE
32
are serially connected to the emitter of the transistor Q
32
in that order. Further, a resistor element RE
31
is connected to the emitter of the transistor Q
31
. The input terminal of an amplifier AMP
31
is connected to a connection point between the emitter of the transistor Q
31
and the resistor element RE
31
and a connection point between the resistor elements RE
32
and RE
33
. The resistor elements RE
31
and RE
32
are connected to each other and the connection point is connected to the output terminal of the amplifier AMP
31
. A voltage output terminal OUT
31
is connected to the output terminal of the amplifier AMP
31
. In the mean time, the amplifier AMP
31
includes plural elements such as a CMOS transistor.
A method to construct a reference voltage supply circuit as described above using a CMOS process is described, for example, in a reference “A Precision Curvature-Compensated CMOS Bandgap Reference:” p634-643 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, No. 6, DECEMBER, 1983.
FIG. 2
is a schematic sectional view showing a resistor and a PNP transistor provided in a conventional reference voltage supply circuit. A resistor and a PNP transistor provided in a conventional circuit are fabricated at the surface of a P
−
-substrate
100
, as shown in FIG.
2
. Two N
−
-wells
101
a
and
101
b
are selectively formed at the surface of a P
−
-substrate
100
. Further, an N
+
-diffused layer
102
a
and a P
+
-diffused layer
102
b
are formed at a surface of the N
−
-well
101
a
. Two terminals
130
b
and
103
c
are connected to the P
+
-diffused layer
102
b
. A well bias terminal
103
a
is connected to the N
+
-diffused layer
102
a
. In such a manner, the resistor element
104
is constructed.
On the other hand, a P
+
-diffused layer
106
and an N
+
-diffused layer
105
are formed at a surface of the N
−
-well
101
b
. An emitter terminal
109
is connected to the P
+
-diffused layer
106
and a base terminal
108
is connected to the N
+
-diffused layer
105
. Further, a P
+
-diffused layer
107
is formed at the surface of a P
−
-substrate
100
at a position so that the N
+
-diffused layer
105
is placed between the P
+
-diffused layers
106
and
107
. A collector terminal
110
is connected to the P
+
-diffused layer
107
. In such a manner, a PNP transistor
111
is constructed.
A process for fabrication of a reference voltage supply circuit including a resistor and a transistor with such constructions has easily been realized in a process for fabrication of a digital circuit including a CMOS transistor which is provided in the amplifier AMP
31
.
However, in a recent fabrication process, in which a gate length of a CMOS transistor is equal to or less than 0.5 &mgr;m, there arises a necessity to reduce a signal delay in a CMOS digital circuit as much as possible. Hence, a resistance lowering technique called Salicide (self aligned silicide) has been applied to electrodes for the gate, source and drain of a MOS transistor.
As a result, a sheet resistance &rgr;S of a resistor element with a resistor of the same width and length is on the order of 10 &OHgr;/□ and magnitudes of a sheet resistance &rgr; S of electrodes for a gate, source and drain have a tendency to further decrease together with future progress in a CMOS transistor process.
On the other hand, a desired value of resistance of a resistor element provided in a reference voltage supply circuit is a very large value in the range of some tens of k&OHgr; to several M&OHgr;. When a large current flows through the base, emitter or collector of a bipolar transistor provided in a reference voltage supply circuit, a voltage drop in diffused layers of the collector, emitter and base including those of electrodes cannot be neglected, if the resistance of the resistor element is lower. That eventually causes undesirable shift from ideal electrical characteristics of a bipolar transistor. Therefore, a current is desired to be small.
In order to fabricate a resistor with a resistance in the range of some tens of k&OHgr; to several M&OHgr; in a recent CMOS semiconductor fabrication process using a Salicide technique, when the resistor is fabricated using an electrode material for a gate, source or drain having a small resistance per a unit area, a length of the resistor is required to be very long on a semiconductor substrate. For example, if a resistor with a resistance of 20 k&OHgr; and a width of 2 &mgr;m is fabricated using a material of &rgr;S =10 &OHgr;/□, a necessary length is as long as 4 mm. That is, a large area is consumed for a resistor element. However, since a fabrication cost per a unit area of a recent CMOS transistor is high, a low resistor material is not suitable for the gate, source or drain of a CMOS transistor.
In such circumstances, there is available a method in which, in order that a resistance of a resistor element is prevented from being lowered without increase in the number of fabrication process steps, an LDD (Lightly Doped Drain) diffused layer is used as a resistor element instead of the resistor shown in FIG.
2
. The LDD diffused layer is introduced in a recent CMOS circuit in order to improve an ability to endure ESD (electrostatic destruction) by preventing local intensification of an electric field in the vicinity of the drain. An LDD diffused layer is formed as a shallow layer at the surface of a semiconductor substrate in a region in which the source and drain are fabricated. A sheet resistance &rgr;S of the LDD diffused layer is several k&OHgr; and the highest value encountered in a recent semiconductor fabrication process.
However, an LDD diffused layer is a very thin layer formed at the surface of a semiconductor substrate and fabricated in an early stage of a fabrication process. Therefore, the LDD diffusion layer has a fault that resistance dispersion thereof becomes large compared with other resistors by influences of surface treatments of the semiconductor substrate after the formation of the layer in the fabrication process such as an etching step. As a result, dispersion of an output voltage in absolute value of a reference voltage supply circuit is larger.
Further, there is also available a method in which, in order that a resistor material with a high sheet resistance is built in a different way, the gate electrode formed on a semiconductor substrate is protected so as not to be transformed to a Salicide and thereby a high resistance is secured.
FIG. 3
is a schematic sectional view showing a resistor and a PNP transistor which are provided
Lattin Christopher
NEC Corporation
Niebling John F.
Whitham Curtis & Christofferson, PC
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