Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-09-29
2004-02-24
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185330, C365S189070, C365S189090, C365S208000, C365S210130
Reexamination Certificate
active
06697282
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of flash memory. More particularly, the present invention relates to a reference voltage generating circuit that may be used in a flash memory.
BACKGROUND OF THE INVENTION
Flash memory is used in a wide variety of products including many types of computing, communication, and consumer electronic devices. Flash memory is a type of nonvolatile memory. Flash memory typically includes one or more memory arrays, each associated with a reference voltage generator. That reference voltage generator comprises two flash cells.
The memory arrays store data values and can be erased, read, and written to. When a read request is made on a particular memory cell within the memory array, the stored data is made available for further processing. This data is usually in the form of an analog signal. Thus, a sensing amplifier is used to detect and amplify this analog signal. The sensing amplifier detects the signal from the memory cell by comparing it to a voltage value from the voltage reference generator array. The reference voltage generator circuit
17
in
FIG. 3
generates a reference value. This circuit
17
will be discussed in greater detail below. The reference voltage generator array
18
takes the output value from reference voltage generator circuit
17
and creates another voltage reference value to be used by the sensing circuit
16
.
Conventionally, flash memory uses the same size flash memory cells for both the array and the reference voltage generator.
FIG. 1
shows a standard flash cell layout used in a conventional reference generating circuit. The standard flash memory cell
10
has a gate width of approximately 0.3 um and a gate length of approximately 0.3 um. It is the same cell used throughout the flash memory array. The flash memory cells in a flash memory array are generally designed to be of minimal size in order to conserve chip die area. In a standard reference generating circuit, the threshold voltage of the device is dependant on factors such as the size of the device and chip process.
FIG. 2
shows a standard flash memory cell
10
configured for programming. The flash memory cell
10
includes select gate
11
, which is connected to a programming voltage VG. Typical programming voltage VG for prior flash memory cells is 12.0 volts supplied by a programming supply VDD. The flash memory cell
10
also includes floating gate
12
, a source
13
, and a drain
14
, wherein the source
13
and the drain
14
are formed in substrate
15
. Both the select gate
11
and floating gate
12
have a width of approximately 0.3 um and a length of approximately 0.3 um as previously mentioned. The memory cell essentially acts as a field effect transistor (“FET”) having a threshold voltage Vt that is variable according to the amount of charge stored on the floating gate
12
.
Applying the programming voltage VG to the select gate
11
switches the FET of the flash memory cell
10
on, causing current to flow from the drain
14
to the source
13
. The programming voltage VG also creates a “vertical” electric field between the substrate
15
and the floating gate
12
. Electron flow in the vertical electric field is depicted as an arrow having its head at floating gate
12
and its tail at substrate
15
. This substantially shows the direction of electron flow in the vertical electric field. As shown, the source
13
is coupled to system ground VSS, and the drain
14
is coupled to a drain voltage VDD. The difference in potential between the drain
14
and the source
13
creates a “horizontal” electric field that accelerates electrons from the source
13
across the channel towards the drain
14
. For one embodiment, it is sufficient for VDD to be 5-7 volts greater than the voltage at source
13
. Electron flow in the horizontal electric field is shown as an arrow having its head at drain
14
and its tail at source
13
. This substantially shows the direction of electron flow across the channel. The accelerated or “hot” electrons collide with the lattice structure of substrate
15
, and some of the hot electrons are swept onto the floating gate by the vertical electric field. In this manner, the amount of charge stored on the floating gate may be increased. The flash memory cell
10
is capable of achieving two or more analog states.
As the flash memory cells
10
for the array are reduced in size, so are the flash memory cells used to make the reference voltage generator. As those cells shrink, however, noise and variation in the process used to fabricate the device may cause the reference voltage generator to perform in an unacceptable manner.
Process variation and/or noise can decrease predictability of the signals generated by the reference voltage generators. This is undesirable given that analog circuits that receive those signals can be highly sensitive to an offset in reference voltage value. For example, if an offset reference voltage is fed to a sensing amplifier, the circuit may read the analog signal and erroneously detect the wrong value resulting in a read failure. In addition, an inaccurate reference voltage may cause excess delay through the sensing circuit leading to read speed failure. Programming time of memory devices may also suffer due to an offset in reference voltage value.
REFERENCES:
patent: 5418743 (1995-05-01), Tomioka et al.
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5764097 (1998-06-01), Whitfield
patent: 6219290 (2001-04-01), Chang et al.
patent: 6432761 (2002-08-01), Gerber et al.
Keeney Stephen N.
Parat Krishna Kumar
Tedrow Kerry D.
Blakely , Sokoloff, Taylor & Zafman LLP
Tran Andrew Q.
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