Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-06-26
2002-03-12
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S553000, C327S525000
Reexamination Certificate
active
06356139
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a reference voltage generator, and more particularly to a reference voltage generator for removing the noise being applied through a ground voltage and adjusting the potential level of the reference voltage.
2. Description of the Related Art
FIG. 1
shows a circuit diagram of a reference voltage generator. The prior reference voltage generator
10
includes PMOS transistors P
1
and P
2
which are respectively connected between a power supply terminal Vcc and nodes Nd
1
and Nd
2
and their gates are commonly connected to the node Nd
2
, NMOS transistors N
1
and N
2
which are respectively connected between the nodes Nd
1
and Nd
2
and a ground terminal Vss and their gates are commonly connected to the node Nd
1
, and a resistor R
1
connected between the node Nd
2
and the ground terminal Vss.
The prior reference voltage generator
10
includes a PMOS transistor P
3
and a NMOS transistor N
3
which are respectively connected between the power supply terminal Vcc and the node Nd
3
and between the ground terminal Vss and a node Nd
3
and a power-up signal PWRUP is commonly supplied to gates thereof and a NMOS transistor N
4
which is connected between the node Nd
2
and the ground terminal Vss and its gate is connected to the node Nd
3
, a NMOS transistor N
5
for a capacitor which is connected between the node N
2
and the ground terminal Vss.
The prior reference voltage generator
10
further includes a PMOS transistor P
4
which is connected between the power supply terminal Vcc and an output node VREF for reference voltage and its gate is connected to the node Nd
2
and a PMOS transistor P
5
for a diode which is connected between the output node VREF and the ground terminal Vss.
The prior reference voltage generator uses Widlar source reference voltage generator.
The operation of the prior reference voltage generator will be described as follows. If the power-up signal PWRUP of low state is received, the PMOS transistor P
3
turns on and the potential of the node Nd
3
becomes in a high state. The NMOS transistor N
4
turns on by the high state potential of the node Nd
3
and the potential of the node Nd
2
becomes in a low state. The PMOS transistors P
1
and P
2
of current mirror structure turn on by the low state potential of the node Nd
2
to provide the power supply Vcc to the nodes Nd
1
and Nd
2
, respectively. The NMOS transistors N
1
and N
2
of current mirror structure turn on by the power supply Vcc at the node Nd
1
to drain the potential of the nodes Nd
1
and Nd
2
to the ground terminal Vss, respectively.
The potential of the node Nd
2
is higher than that of the node Nd
1
by the resistor R
1
connected between the NMOS transistor N
2
and the ground terminal Vss. But, because the potential of the node Nd
2
is drained to the ground terminal Vss through the NMOS transistor N
4
, the node Nd
2
becomes in a low state. Accordingly, the PMOS transistor P
4
which receives the potential of the node Nd
2
as an input of its gate turns on and the power supply Vcc is provided to the output node VREF as the reference voltage. The PMOS transistor P
5
also turns on by the potential of the output node VREF. Accordingly, the power supply voltage Vcc is voltage-divided by the PMOS transistors P
4
and P
5
connected between the power supply terminal Vcc and the ground terminal Vss and the divided voltage is provided to the output node as the voltage reference VREF.
In the above prior reference voltage generator, when a chip operates, the noise caused in the ground terminal is transferred to the output node for reference voltage VREF as it is as the simulation result shown in FIG.
2
. It is apt to cause the malfunction when the data signal having a TTL level is compared with the reference VREF. Besides, there is no solution after metal revision, in case where the level of the reference voltage VREF is shifted by the process variation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a reference voltage generator for removing the noise caused in the ground terminal using a low pass filter and for adjusting the potential level of the reference voltage.
According to an aspect of the present invention, there is provided to a reference voltage generator, comprising: reference voltage generation means for generating a reference voltage having a potential level through an output node by a power-up signal; noise removing means for a noise which is caused in a ground terminal and is provided to the output node; and reference voltage level adjusting means being connected between the output node of the reference voltage generation means and the ground terminal and for adjusting the potential level of the reference voltage from the reference voltage generation means using plural metal options and fuse options.
In the reference voltage generator, the noise removing means includes a capacitor and a resistor. The capacitor is comprised of a MOS transistor, for example NMOS transistor.
In the reference voltage generator, the reference voltage level adjusting means includes: a first fuse decoder for generating first and second output signals decoded in accordance with a cutting state of a first fuse; a second fuse decoder for generating third and fourth output signals decoded in accordance with a cutting state of a second fuse; a fuse multiplexor for receiving the first to the fourth output signals from the first and second fuse decoders to generate a first to a fourth control signals; voltage adjusting means including a first switching stage being switched by the first to fourth control signals from the fuse multiplexor and being connected to metal options; a second switching stage being switched by the first to fourth control signals from the fuse multiplexor and being connected to metal options and a third switching stage being switched by the first to the fourth control signals; and selective logic means for selectively controlling the third switching stage by the first to the fourth control signals.
In the reference voltage generator, each of the first fuse decoder and the second fuse decoder includes; a first or second fuse connected between a power supply terminal and a first node; a first NMOS transistor for a capacitor connected between the first node and the ground terminal; a second NMOS transistor which is connected between the first node and the ground terminal and its gate is connected to a second node; a first inverter including a first PMOS transistor and a third NMOS transistor which are connected between the power supply terminal and the ground terminal and their gates are commonly connected to the first node; a second inverter including a second PMOS transistor and a fourth NMOS transistor which are connected between the power supply terminal and the ground terminal and their gates are commonly connected to the second node and providing a second or fourth output signal through a third node; a third inverter including a third PMOS transistor and a fifth NMOS transistor which are connected between the power supply terminal and the ground terminal and their gates are commonly connected to the third node and their gates are connected to the third node and providing a first or third output signal.
In the reference voltage generator, the fuse multiplexor includes: a first NAND gate for receiving the first output signal from the first fuse decoder and the third output signal from the second fuse decoder to generate the first control signal; a second NAND gate for receiving the second output signal from the first fuse decoder and the third output signal from the second fuse decoder to generate the second control signal; a third NAND gate for receiving the first output signal from the first fuse decoder and the fourth output signal from the second fuse decoder to generate the third control signal; a fourth NAND gate for receiving the second output signal from the first fuse decoder and the fourth output signal from the second fuse decoder to generate the fourth c
Callahan Timothy P.
Hyundai Electronics Industries Co,. Ltd.
Nguyen Hai L.
Pillsbury Winthrop LLP Intellectual Property Group
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