Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-02-20
2004-04-27
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S513000
Reexamination Certificate
active
06727744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a reference voltage generator for generating a reference voltage using a bandgap voltage.
2. Description of the Related Art
The reference voltage generator has a current supply unit comprising first through third P channel MOS (hereinafter abbreviated as “PMOS”) transistors, first and second N channel MOS (hereinafter abbreviated as “NMOS”) transistors, and a first resistor.
The sources of the first and second PMOS transistors are connected to a source potential VDD, and the gates thereof are connected in common. The drain of the first PMOS transistor is connected to the drain and gate of the first NMOS transistor. The source of the first NMOS transistor is connected to a ground potential GND. The drain of the second PMOS transistor is connected to the gates of the first and second PMOS transistors and the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the ground potential GND through a resistor.
The source and gate of the third PMOS transistor, which constitutes a current mirror with respect to the second PMOS transistor, are respectively connected to the source potential VDD and the gates of the first and second PMOS transistors. The drain of the third PMOS transistor is connected to the collector of a PNP transistor through a second resistor. The base and emitter of the PNP transistor are respectively connected to the ground potential GND. A reference voltage VREFO is outputted from a point A where the drain of the third PMOS transistor and the second resistor are connected.
In the present reference voltage generator, a current Ia that flows through the second PMOS transistor, is expressed as given by the following equation (1) assuming that the mutual conductances of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are respectively given as gm
1
, gm
2
, gm
3
and gm
4
:
Ia
=
[
(
kT
/
q
)
ln
{
(
gm1
×
gm4
)
/
(
gm3
×
gm2
)
}
]
/
R5
=
KT
/
R5
(
1
)
where K=(k/q) ln{(gm
1
×gm
4
)/(gm
3
×gm
2
)}
Incidentally, T indicates an absolute temperature, k and q indicate positive constants, and R
5
indicates the resistance value of the first resistor, respectively.
A current Ib that flows through the third PMOS transistor constituting the current mirror with respect to the second PMOS transistor, is expressed as given by the following equation (2) assuming that the mutual conductance of the third PMOS transistor is given as gm
6
:
Ib=Ia×
(
gm
6
/gm
3
) (2)
Thus, the reference voltage VREFO outputted to the connecting point A is expressed as given by the following equation (3) assuming that the resistance value of the second resistor is given as R
7
and a base-to-emitter voltage of the PNP transistor is given as VBE:
VREF
0
=
Ib×R
7
+
VBE
(3)
Substituting the equations (1) and (2) for the first term of the equation (3) yields the following equation (4):
VREF
0
=
KT
(
gm
6
/gm
3
)(
R
7
/R
5
)+
VBE
(4)
Since the first and second resistors are formed in the same process, they have the same temperature characteristics. Therefore, (R
7
/R
5
) in the first term of the equation (4) does not depend on the temperature. The first term thereof has a positive temperature coefficient proportional to the absolute temperature T. On the other hand, the base-to-emitter voltage VBE of the second term has a negative temperature coefficient. Thus, the reference voltage generator is capable of generating the reference voltage VREFO with no change in temperature according to suitable adjustments to the resistance vales R
5
and R
7
and the mutual conductances gm
1
through gm
4
.
The base-to-emitter voltage VBE of the PNP transistor normally has a negative temperature characteristic of about −2 mV/° C. Thus, the (Ib×R
7
) has to assume a positive temperature characteristic of +2 mV/° C. in order to avoid a temperature change in the reference voltage VREF
0
. Namely, there is a need to meet &Dgr;Ib×R
7
=2 mV assuming that the amount of a change in current Ib per 1° C. is given as &Dgr;Ib.
Therefore, &Dgr;Ia results in about 0.2 nA assuming that, for example, R
5
=1 M&OHgr;, (gm
1
×gm
3
)/(gm
3
×gm
2
)=10, and Ia=Ib. Accordingly, the resistance value R
7
of the second resistor results in 2 mV/0.2 nA=10M&OHgr;. A very large resistance (i.e., large circuit area) is thus required.
On the other hand, there are three methods of {circle around (1)} reducing the resistance value R
5
, {circle around (2)} increasing (gm
1
×gm
3
)/(gm
3
×gm
2
) and {circle around (3)} increasing the current mirror of Ib/Ia with a view to reducing the resistance value R
7
. Since, however, any of them is a method of increasing a current to thereby increase the amount of a change in current per 1° C., current consumption increases.
Thus, a trade-off between the current consumption and the circuit area is required to generate the reference voltage VREF
0
free of the change in temperature. It is therefore difficult to configure such a reference voltage generator as to simultaneously meet low current consumption and a small circuit area.
SUMMARY OF THE INVENTION
The present invention aims to provide a reference voltage generator reduced in current consumption and small in circuit area.
With a view toward solving the foregoing problem, a first invention of the present inventions provides a reference voltage generator comprising a current supply unit for supplying a current corresponding to the value of a first resistor to an output node, and a transistor supplied with the current from the output node through a second resistor, wherein the sum of a voltage developed across the second resistor and a voltage developed in the transistor is outputted from the output node as a reference voltage, and the second resistor has a temperature coefficient larger than the first resistor.
REFERENCES:
patent: 6437614 (2002-08-01), Chen
patent: 6529066 (2003-03-01), Guenot et al.
patent: 6605988 (2003-08-01), Gauthier et al.
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Zweizig Jeffrey
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