Reference voltage generation scheme for gate oxide protected cir

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327538, 323313, 323314, G05F 302

Patent

active

059232110

ABSTRACT:
A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.

REFERENCES:
patent: 5359552 (1994-10-01), Dhong et al.
patent: 5384739 (1995-01-01), Keeth
patent: 5506541 (1996-04-01), Herndon
patent: 5545979 (1996-08-01), Nukui et al.
patent: 5712590 (1998-01-01), Dries et al.

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