Reference voltage generation circuit having reduced...

Details Reference voltage generation circuit having reduced... Reference voltage generation circuit having reduced...

2001-09-27

2003-07-08

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S538000

Reexamination Certificate

active

06590445

ABSTRACT:

CROSS REFERENCE TO A RELATED APPLICATION
This application claims priority under 35 USC §119 to Japanese Patent Application No. 2000-294287 filed on Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
The present invention generally relates to an electrical power source apparatus for use in a small instrument such as a mobile phone, and in particular to a CMOS (Complementary Metal Oxide Semiconductor) inclusion reference voltage generation circuit used alone or built in another semiconductor apparatus, a method for adjusting its output value, and an electrical power source that applies such a reference voltage generation circuit.
BACKGROUND OF THE INVENTION
A reference voltage generation circuit that employs a depletion type MOS transistor whose gate is connected to a source as a constant current source has been known as described for example in Japanese Patent Application Laid Open No. 04-65546. In such a description, as demonstrated in
FIG. 9
, a constant current characteristic is utilized while connecting the gate to the source in a depletion type MOS transistor Q
1
. In addition, a plurality of enhancement type MOS transistors Q
12
and Q
13
, each having a gate and a drain connected to each other, is serially connected to be driven by the constant current. Then, voltages generated in these MOS transistors Q
12
and Q
13
can be taken out as reference voltages. Any one of such MOS transistors Q
1
, Q
12
, and Q
13
are of an n-channel type. Voltages (Vgs) between the gate and source of the MOS transistors Q
12
and Q
13
are V
0
12
and V
0
13
, respectively. Only one or two or more MOS transistors Q
12
and Q
13
can be employed as demonstrated in FIG.
9
.
In such a circuit, the threshold voltages of respective enhancement type MOS transistors Q
12
and Q
13
are differentiated from each other. However, as a manner of differentiating threshold voltages among the depletion type MOS transistor Q
1
and the enhancement between the MOS transistor Q
12
and/or Q
13
, it is described that impurity density of either a base plate or a channel is changed as an example. Such a manner is performed by changing an infusion value when an ion is infused.
Another reference voltage generation circuit that promises a depletion type MOS transistor whose gate is connected to a constant current source is demonstrated in FIG.
10
. The legend Q
1
indicates a depletion type MOS transistor that is the same as described in FIG.
9
. The legend Q
2
indicates an enhancement type MOS transistor whose threshold voltage is lower (i.e., threshold voltage Vth(low)). The legend Q
3
indicates an enhancement type MOS transistor whose threshold voltage is higher (i.e., threshold voltage Vth(high)). As a reference voltage (VREF), a difference between threshold voltages of respective enhancement type MOS transistors Q
2
and Q
3
is output.
FIG. 11
demonstrates a plurality of relations between the (Vgs) and the (Ids)
½
of the MOS transistors Q
1
, Q
2
, and Q
3
of the reference voltage generation circuit illustrated in
FIG. 10
using signals under a condition that a drain voltage is saturated. In the above, it is premised that all of conductance factors (K) of the respective MOS transistors Q
1
, Q
2
, and Q
3
, are the same and the legend “Vgs” represents a voltage between a gate and a source. In addition, the legend “Ids” represents a drain current.
Since the Vgs of the MOS transistors Q
1
is fixed to zero volts, a constant current “Iconst” is carried in accordance with the legend Q
1
of FIG.
11
. Accordingly, respective “Vgs” of the MOS transistors Q
2
and Q
3
wherein the Ids becomes the Iconst (Ids=Iconst) amount to V
0
2
and V
0
3
. Since the reference voltage VREF is represented by this difference, the following formulas are established:
VREF=V
0
3
−
V
0
2
=
Vth
(high)−
Vth
(low)
Accordingly, it can be understood therefrom that the reference voltage VREF can be represented by the difference between threshold voltages Vth(high) and Vth(low) of the pair of the MOS transistors Q
2
and Q
3
.
A reference voltage VREF formed by such a circuit configuration has the following advantages. Since the reference voltage is determined by a difference between threshold voltages Vth, unevenness of the reference voltage VREF is smaller than a change in a constant current caused by unevenness of threshold voltage Vth of the depletion type MOS transistor. Second, since temperature characteristics of the MOS transistors Q
2
and Q
3
are substantially the same, sensitivity of the reference voltage VREF to temperature is small. Third, when comparing with a band gap reference circuit, since at least three MOS transistors are enough to constitute a reference voltage generation circuit, the reference voltage generation circuit can readily be configured within a relatively small area. The band gap reference circuit is a device that takes out a reference voltage VREF having an extraordinary small temperature coefficient by utilizing a difference in polarity of temperature performance between a voltage (Vbe: a voltage between a base and an emitter) of a PN connection type and a thermal voltage Vt. The thermal voltage Vt should be obtained by dividing KT into (q) (i.e., kT/q), wherein (k) represents a Boltzman constant, (T) represents an absolute temperature, and (q) represents a unit of electricity.
However, even by the circuit configuration of
FIG. 10
, there exists the following problems when achieving a reference voltage VREF having higher precision. First, since ion infusion determines respective threshold voltages Vth of MOS transistors Q
2
and Q
3
, these unevenness are independent from each other, and the difference therebetween becomes larger. As a result, unevenness of the reference voltage VREF becomes larger.
FIG. 12
demonstrates an example when the threshold Vth of the MOS transistor Q
2
becomes low and that of the MOS transistor Q
3
becomes high, wherein each of dotted lines represents a status before a change.
Second, since respective channel impurity profiles are different from each other, respective threshold voltages Vth and temperature performances of mobility are different from each other in a strict sense. As a result, there is a limit on improvement in a temperature performance of the reference voltage VREF.
FIG. 13
demonstrates another example when temperature is high and the threshold voltages Vth and the mobilities of the MOS transistors Q
2
and Q
3
are changed. The dotted line therein represents a condition before a change. As noted therefrom, inclination varies.
Third, when describing a conventional process of a semiconductor apparatus provided with a reference voltage generation circuit with reference to
FIG. 14
, a well is formed on a wafer (in step S
22
) after that wafer is set (in step S
21
), and an element separation coat is then formed on the wafer surface (in step S
23
). Some ions are infused in an element area so as to determine a threshold voltage Vth, thereby a reference voltage VREF is determined (in step S
24
). After forming a gate electrode on the surface of the wafer (in step S
25
), and the source and drain on the element area (in step S
26
), an insulating coat (e.g. a polysilicon-metal insulating coat) is formed between a poly-silicon and a metal wiring (in step S
27
). Then, one or more contact holes are formed on the poly-metal insulating coat (in step S
28
). After forming a metal wiring on the polysilicon-metal insulating coat (in step S
29
), a passivation coat is formed (in step S
30
). A wafer test is then performed (in step S
31
), and a package is sealed, thereby a semiconductor apparatus is completed (in step S
32
).
However, in such a conventional reference voltage generation circuit, since the reference voltage VREF is determined by the threshold voltage Vth, when an ion infusion process that determines the threshold voltage Vth (refer to FIG.
14
and step S
4
) is over, the reference voltage VREF can not be changed. In addition, since such an ion infus

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