Reference voltage generating circuit for enhancement/depletion M

Details Reference voltage generating circuit for enhancement/depletion M Reference voltage generating circuit for enhancement/depletion M

1985-08-20

1987-11-24

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307263, 307268, 307574, H03K 1716, H03K 19017, H03K 512, H03K 17687

Patent

active

047091681

ABSTRACT:
A reference voltage generating circuit comprises a depletion type MOS transistor of which the gate and the drain are connected to a power source and an enhancement type MOS transistor of which the gate and the drain are connected to the source of the depletion type MOS transistor through a junction from which a reference voltage is outputted. This reference voltage is adapted to be applied to the gate of an enhancement type MOS transistor in a load circuit composed of enhancement/depletion MOS transistors and serving to drive a logical circuit.

REFERENCES:
patent: 4307308 (1981-12-01), Sano
patent: 4423339 (1983-12-01), Seelbach et al.
patent: 4450369 (1984-05-01), Schuermeyer
patent: 4451744 (1984-05-01), Adam
patent: 4490632 (1984-12-01), Everett et al.
patent: 4568844 (1986-02-01), O'Connor

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