Reference voltage generating circuit

Details Reference voltage generating circuit Reference voltage generating circuit

1998-10-26

2001-02-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S543000, C323S314000, C323S315000

Reexamination Certificate

active

06184745

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reference voltage generating circuit, and more particularly to a MOS-type reference voltage generating circuit.
2. Description of the Background Art
FIG. 1
illustrates a conventional reference voltage generating circuit using a voltage difference Vgs between a gate and a source of an NMOS transistor.
First and second PMOS transistors P
11
, P
12
constitute a current mirror and first and second NMOS transistors N
11
, N
12
are respectively connected between each drain of the first and second PMOS transistors P
11
, P
12
and a ground. A back-bias voltage Vbb is applied to each substrate of the first and second NMOS transistors N
11
, N
12
for the purpose of effectively diminishing a threshold voltage change, and gates of the first and second NMOS transistors N
11
, N
12
are commonly connected to an output node A.
The operation of the thusly constructed reference voltage generating circuit will be described hereinafter with reference to the accompanying drawings.
In
FIG. 1
, each of the PMOS transistors P
11
, P
12
has the identical length and width. On the other hand, the NMOS transistors N
11
, N
12
have the same length but a width of the first NMOS transistor N
11
is greater than that of the second NMOS transistor N
12
(W
n11
>W
n12
). Here, it is assumed that the ratio of the width of the first NMOS transistor N
11
and that of the second NMOS transistor N
12
is K (K=W
n11
/W
n12
), and currents towards the NMOS transistors N
11
, N
12
are indicated as I
n11
, I
n12
, respectively.
On such an assumption, an operation current applied to the output node A from the NMOS transistors N
11
, N
12
may be represented by a following equation (1).
Iop
=
Vgs
⁡
(
N12
)
-
Vgs
⁡
(
N11
)
R1
(
1
)
Here, Vgs(N
12
) denotes a voltage difference between the gate and source of the NMOS transistor N
12
and Vgs(N
11
) is a voltage difference between the gate and source of the NMOS transistor N
11
.
If the NMOS transistors N
11
, N
12
operate in a saturation region, each of the currents I
n11
, I
n12
, which are applied to the first and the second NMOS transistors N
11
, N
12
, respectively, may be expressed as follows.
I
N11
=
β
1
2
⁡
[
Vgs
⁡
(
N12
)
-
Vtn
]
2
=
β
1
2
⁡
[
Vref1
-
V
B
-
Vtn
]
(
2
)
I
N12
=
β
2
2
⁡
[
Vgs
⁡
(
N11
)
-
Vtn
]
2
=
β
2
2
⁡
[
Vref1
-
Vtn
]
(
3
)
Here, Vtn denotes a threshold voltage of the NMOS transistors N
11
, N
12
, V
B
denotes a voltage of a node B (V
B
=I
N11
×R
1
), and each of &bgr;
1
, &bgr;
2
which are the process parameters represents a transconductance. In addition, it is noted that
β
=
U
N
⁢
ϵ
t
ox
⁢
(
W
L
)
,
wherein U
N
is electronic mobility of each of the NMOS transistors, &egr; is a dielectric constant, and t
ox
is a gate oxide thickness.
Thus, by virtue of the current mirror operation of the PMOS transistors P
11
, P
12
, when equalizing the values of the currents I
n11
, I
n12
, being applied to the NMOS transistors N
11
, N
12
, respectively, an equation (4) can be obtained from the equations (2) and (3).
Vref
-
Vtn
=
K
·
I
N11
⁢
R1
H
-
1
,

⁢
K
=
β
1
β
2
(
4
)
Accordingly, the operation current (I
OP
=I
N11
=I
N12
), and a reference voltage Vref can be represented with each of equations as follows.
I
op
=
2
R1
2
⁢
β
1
⁢
(
K
-
1
)
2
(
5
)
Vref
=
Vtn
+
2
R1
·
β
2
⁢
(
1
-
1
K
)
(
6
)
Thus, according to the equation (6), since the reference voltage Vref is determined by the threshold voltage Vtn, resistance R
1
, the process parameter &bgr;
2
, and a constant K, the reference voltage Vref may be generated irrespective of any change of a power supply voltage Vcc.
In addition, an effect of a temperature change on the reference voltage Vref may appear dependently upon a temperature change of each of the above parameters. Namely, the threshold voltage Vtn generally has −1 mV/° C. of a temperature dependency, and the resistance R of which a gate is formed of a doped polysilicon has +0.01/° C. thereof. Also, the electronic mobility U
N
varies by
T
-
3
2
each time in accordance with temperature, and thus the process parameter &bgr;
2
also shows
T
-
3
2
of a temperature dependency.
Accordingly, when
2
R1
·
β
2
⁢
(
1
-
1
K
)
is to have +1 mV/° C. of the temperature dependency, the reference voltage Vref can be generated, regardless of any temperature change.
In the conventional reference voltage generating circuit, however, the threshold voltage Vtn of the NMOS transistors N
11
, N
12
may vary in accordance with the back-bias voltage Vbb which is applied to the corresponding substrates of the first and second NMOS transistors N
11
, N
12
.
That is to say, a bulk of each of the NMOS transistors N
11
, N
12
is connected to a p-type substrate and the p-type substrate is biased at a negative back-bias voltage Vbb which is generated inside a chip device. Accordingly, the back-bias voltage Vbb generates a voltage difference Vsb between the source and the bulk of each of the NMOS transistors N
11
, N
12
, and thus has an effect on the threshold voltage Vtn as a following equation (7).
Vtn=Vtn
0+&ggr;
{square root over (Vsb)}
  (7)
In the equation (7), Vtn
0
is the value of the threshold voltage Vtn when Vsb=0, &ggr; is a body effect factor which has a value of the range between 0.4 to 1.2 according to doping condition, and Vsb is the voltage difference between the source and the bulk of the NMOS transistor.
FIG. 2
is a graph which illustrates a change of the threshold voltage Vtn in accordance with which the back-bias voltage Vbb varies, and shows that as an absolute value of the back-bias voltage Vbb increases, the threshold voltage Vtn thus correspondingly increases.
FIG. 3
is a graph illustrating a simulation result which shows a change of the reference voltage Vref with respect to the back-bias voltage Vbb. The reference voltage Vref is not considerably affected by the change of the power supply voltage Vcc when the back-bias voltage Vbb is uniformly maintained; however, when the back-bias voltage Vbb changes, the voltage Vref accordingly has a dependency of +178 mV/V. Moreover, since the back-bias voltage Vbb is generally equivalent to −½ of the power supply voltage Vcc, the absolute value of the back-bias voltage Vbb also increases as the power supply voltage Vcc increases. As a result, when the absolute value of the back-bias voltage Vbb increases, the threshold voltage Vtn increases in accordance therewith and thus the reference voltage Vref consequently increases, which leads to the problem.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a reference voltage generating circuit that substantially obviates at least one of the problems or disadvantages of the conventional art.
Another object of the present invention is to provide a reference voltage generating circuit that generates an uniform reference voltage regardless of any change of a back-bias voltage by using a voltage difference between a gate and a source of a PMOS transistor.
To achieve at least the above-described objects in a whole or in parts, there is provided a reference voltage generating circuit according to the present invention that includes a reference voltage generating unit for generating a first reference voltage with respect to a power supply voltage, and a level converting unit for converting the first reference voltage supplied from the reference voltage generating unit to a second reference voltage with respect to a ground voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide a further explanation of the invention as claimed.


REFERENCES:
patent: 4935690 (1990-06-01), Yan
patent: 5077518 (1991-12-01), Han
patent: 5173656 (1992-12-01), Seevinck et al.
patent: 5204612 (1993-04-01)

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