Reference voltage generating circuit

Details Reference voltage generating circuit Reference voltage generating circuit

1982-10-29

1984-05-01

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

323313, G05F 316

Patent

active

044463839

ABSTRACT:
A reference voltage generating circuit comprising a depletion mode FET transistor connected to provide a constant current source coupled between a supply voltage and an output node. Three serially connected enhancement mode FET transistors are connected between the output node and a reference voltage. The first enhancement mode device is diode coupled to provide an enhancement threshold voltage offset, the second enhancement mode device has its gate electrode connected to the supply voltage to compensate for variations in supply voltage and the third enhancement device has its gate electrode connected to a source follower circuit. The source follower circuit comprises two serially connected depletion mode devices which receive an input from the output node and provide a feedback output to the gate electrode of the third enhancement mode device so that a constant voltage of a predetermined magnitude is maintained at the output node.

REFERENCES:
patent: 3806742 (1974-04-01), Powell
patent: 3970875 (1976-07-01), Leehan
patent: 4016434 (1977-04-01), DeFillippi
patent: 4135125 (1979-01-01), Oura
patent: 4158804 (1979-06-01), Butler et al.
patent: 4300061 (1981-11-01), Mihalich et al.
Hansen, "Voltage Regulator", IBM Tech. Discl. Bull.; vol. 14, No. 4, pp. 1050; 9/1971.
IBM TDB Article, "Low Output Impedance Reference Voltage," Spina et al., vol. 22, No. 11, Apr. 1980, pp. 5017-5018.
IBM TDB Article, "Voltage Reference Circuit," R. S. Becker, vol. 23, No. 5, Oct. 1980, pp. 1840-1841.

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