Reference scheme for a non-volatile semiconductor memory device

Details Reference scheme for a non-volatile semiconductor memory device Reference scheme for a non-volatile semiconductor memory device

2007-08-21

2007-08-21

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

11145520

ABSTRACT:
A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory cell. In the circuitry area, additional main reference cells are provided, which are configured to also have a threshold voltage corresponding to an erased or programmed state of a memory cell. The main reference cells are used for setting of said array reference cells and said array reference cells are provided as a reference for reading or writing a state of said memory cells. A method is also provided for setting array reference cells in a non-volatile semiconductor memory device to a predefined threshold voltage.

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