Reference level generator and memory device using the same

Details Reference level generator and memory device using the same Reference level generator and memory device using the same

2000-07-20

2003-01-21

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S053000

Reexamination Certificate

active

06509787

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a reference level generator in a memory device.
2. Background of the Related Art
A ferroelectric memory, i.e., an FRAM (Ferroelectric Random Access Memory), has in general a data processing speed similar to a DRAM dynamic Random Access Memory) which is used widely as a semiconductor memory. Because the FRAM can conserve data even if the power is turned off, much attention has been given to FRAM as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 1
illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material. A polarization induced by an electric field is not erased, but a certain amount (‘d’ and ‘a’ states) remains, even if the electric field is removed owing to existence of the residual polarization (or spontaneous polarization). The ‘d’ and ‘a’ states correspond to ‘1’ and ‘0’, respectively, in application to memories.
FIG. 2
illustrates a system of unit cell of the related art non-volatile ferroelectric memory. The system of a unit cell of the related art non-volatile ferroelectric memory is provided with a bitline BL formed in one direction, a wordline W/L formed in a direction perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T
1
having a gate connected to the wordline W/L and a source connected to the bitline BL, and a ferroelectric capacitor FC
1
having a first terminal connected to a drain of the transistor T
1
and a second terminal connected to the plateline P/L.
FIG. 3A
illustrates a timing diagram of a write mode operation of the related art ferroelectric memory. In a writing mode, when an external chip enable signal CSBpad changes from ‘high’ to ‘low’ and a write enable signal WEBpad changes from ‘high’ to ‘low’ simultaneously, the write mode is enabled or initiated. When an address decoding is started in the write mode, a pulse applied to a relevant wordline is transited from ‘low’ to ‘high’ to select a cell. Thus, during a period the wordline is held ‘high’, a relevant plateline has a ‘high’ signal applied thereto for one period and a ‘low’ signal applied thereto for the other period in succession.
In order to write a logical value ‘1’ or ‘0’ on the selected cell, a ‘high’ or ‘low’ signal synchronized to the write enable signal WEBpad is applied to a relevant bitline. If a ‘high’ signal is applied to the bitline and a signal applied to the plateline is ‘low’ in a period in which a signal applied to the wordline is ‘high’, a logical value ‘1’ is written on the ferroelectric capacitor. If a ‘low’ signal is applied to the bitline and a signal applied to the plateline is ‘high’, a logical value ‘0’ is written on the ferroelectric capacitor.
The operation for reading the data stored in the cell by the aforementioned write mode operation will be explained.
FIG. 3B
illustrates a timing diagram of a read mode operation of the related art ferroelectric memory. If the chip enable signal CSBpad changes from ‘high’ to ‘low’ from outside of the chip, all bitlines are equalized to a ‘low’ voltage before a relevant wordline is selected. After the bitlines are disabled, an address is decoded, and the decoded address causes a ‘low’ signal on a relevant wordline to transit to a ‘high’ signal, to select a relevant cell. A ‘high.’ signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value ‘1’ stored in the ferroelectric memory. If a logical value ‘0’ is in storage in the ferroelectric memory, a data corresponding to the logical value ‘0’ is not broken. As the data not broken and the data broken provide values different from each other according to the aforementioned hysteresis loop, the sense amplifier can sense a logical value ‘1’ or ‘0’.
The case of the data broken is a case when the value is changed from ‘d’ to ‘f’ in the hysteresis loop of
FIG. 1
, and the case of the data not broken is a case when the value is changed from ‘a’ to ‘f’ in the hysteresis loop of FIG.
1
. Therefore, if the sense amplifier is enabled after a certain time period has passed, in the case of the data broken, a logical value ‘1’ is provided as amplified, and in the case of the data not broken, a logical value ‘0’ is provided. After the sense amplifier provides the data and since an original data should be restored, the plateline is disabled from ‘high’ to ‘low’ in a state a ‘high’ signal is applied to a relevant wordline.
FIG. 4
illustrates a block diagram of a related art nonvolatile ferroelectric memory. The related art nonvolatile ferroelectric memory is provided with a main cell array
41
having a lower portion allocated for a reference cell array
42
, a wordline driver
43
on one side of the main cell array
41
for providing a driving signal to the main cell array
41
and the reference cell array
42
, and a sense amplifier unit
44
formed under the main cell array
41
. The wordline driver
43
provides a driving signal to the main wordline for the main cell array
41
and the reference wordline for the reference cell array
42
. The sense amplifier unit
44
has a plurality of sense amplifiers each for amplifying bitlines and bitbarlines.
The operation of the aforementioned nonvolatile ferroelectric memory will be explained with reference to
FIG. 5
, which illustrates a partial detail of
FIG. 4
, wherein the main cell array has a folded bitline structure. The reference cell array
42
also has a folded bitline structure, and two pairs of a reference cell wordline and a reference cell plateline are provided, which are defined as RWL_
1
, RPL_
1
and RWL_
2
, RPL_
2
. . . RWL_N−1, PRL_N−1, and RWL_N, RPL_N, respectively.
Provided that the main cell wordline MWL_N−1 and the main cell plateline MPL_N−1 is enabled, the reference cell wordline RWL_N−1 and the reference cell plateline RPL_N−1 are enabled. Therefore, a data from the main cell is loaded on the bitline BL, and a data from the reference cell is loaded on the bitbarline /BL. When the main cell wordline MWL_N and the main cell plateline MPL N are enabled, the reference cell wordline RWL_N and the reference cell plateline RPL_N are also enabled. Therefore, a data from the main cell is loaded on the bitbarline /BL, and a data from the reference cell is loaded on the bitline BL. In this instance, a bitline level REF caused by the reference cell is between bitline levels B_H(High) and B_L (Low) caused by the main cell.
In order to position the reference voltage REF between the bitline levels B_H and B_L, two reference cell operation methods can be used. The first method stores logic “1” in the capacitor of the reference cell, which can be achieved by providing a capacitor of a reference cell of which size is smaller than a capacitor size of the main cell. The second method stores a logic “0” in the capacitor of the reference cell, which can achieved by providing a capacitor of a reference cell of which size is larger than a capacitor size of the main cell. Thus, the related art nonvolatile ferroelectric memory can produce a reference voltage required by the sense amplifier unit
44
by using the foregoing two methods.
However, the aforementioned related art nonvolatile ferroelectric memory has various problems. For example, when a capacitor size of the reference cell is made smaller than a capacitor size of the main cell as the first method for providing a level of the reference voltage to be between the bitline levels B_H and B_L, when the reference cell capacitor is excessively switched, i.e., destructed, in comparison to the main cell, the reference cell experiences fatigue before the main cell, which can lead to an unstable reference

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