Reference generator circuit for BiCMOS ECL gate employing PMOS l

Details Reference generator circuit for BiCMOS ECL gate employing PMOS l Reference generator circuit for BiCMOS ECL gate employing PMOS l

1993-02-22

1994-04-26

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072967, 307475, 307455, H03K 1902, H03K 19086

Patent

active

053069641

ABSTRACT:
A reference circuit for coupling to a particular type of BiCMOS logic gate includes a V.sub.be multiplier coupled between V.sub.CC and a first internal node. The multiplier establishes a predetermined potential at the internal node which determines the voltage swing across the PMOS load devices utilized in the BiCMOS logic gate. A first PMOS transistor, configured as a current source within the multiplier, has its source coupled to the internal node. A second PMOS transistor has its gate coupled to the gate and drain of the first PMOS transistor in a source-follower configuration so as to drive the source node of the second PMOS transistor to the predetermined potential. A reference PMOS transistor is coupled between V.sub.CC and the source node of the second PMOS transistor, with the gate of the reference PMOS transistor being commonly coupled to the gates of the PMOS load devices and to a reference potential. A NMOS current source device is coupled to the source of the second PMOS transistor such that a reference current flows through the reference PMOS transistor; this current is then mirrored through the PMOS load devices of the BiCMOS logic gate.

REFERENCES:
patent: 4128816 (1978-12-01), Shimotsuma
patent: 4593208 (1986-06-01), Single
patent: 4794317 (1988-12-01), van Tran
patent: 5001362 (1991-03-01), Tran
patent: 5034626 (1991-07-01), Pirez et al.
patent: 5197358 (1993-01-01), Martin

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