Reference frequency and facet to facet error correction circuit

Details Reference frequency and facet to facet error correction circuit Reference frequency and facet to facet error correction circuit

1999-12-21

2000-11-21

Phan, James

Optical: systems and elements

Deflection using a moving element

Using a periodically moving element

359217, 359900, 347249, 347250, G02B 2608

Patent

active

061511528

ABSTRACT:
A reference frequency and facet to facet correction circuit utilizes a phase locked loop which includes a digital phase detector to measure the time difference between the end of scan and the end of count of each facet and store them in a lookup table. The phase locked loop continuously generates an average time value form the time differences of all the facets of the polygon. The phase locked loop also adds the errors of each facet to the average time value and uses the result to correct the frequency of a pixel clock generator for both the reference frequency and facet to facet errors.

REFERENCES:
patent: 4704698 (1987-11-01), Reiniger
patent: 4821048 (1989-04-01), Hornig et al.
patent: 5541637 (1996-07-01), Ohashi et al.

Affiliated with

Also associated with

Rating

Reference frequency and facet to facet error correction circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reference frequency and facet to facet error correction circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reference frequency and facet to facet error correction circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1263533