Reference-free clock generator and data recovery PLL

Details Reference-free clock generator and data recovery PLL Reference-free clock generator and data recovery PLL

1999-12-23

2001-10-23

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S150000, C327S159000

Reexamination Certificate

active

06307413

ABSTRACT:

FILED OF THE INVENTION
The present invention relates to clock and data recovery in a phase-lock loop (PLL) generally and, more particularly, to a method and/or architecture for a linear data clock and recovery of half-rate clock signals (e.g., 0 and 90 degree phases) from a serial input data stream.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional circuit
10
for performing clock and data recovery in a serial data communication device is shown. The circuit
10
requires a reference clock and a clock difference detector. The circuit
10
comprises a half-rate VCO
12
, a divider
14
, a feedback (FB) divider
15
, a frequency difference detector (FDD)
16
, a half-rate phase detector (PD)
18
, a phase-frequency detector (PFD)
20
, a multiplexer
22
and a charge pump filter (CPF)
24
. The VCO
12
presents signals from a number of outputs
26
a
-
26
n
to a number of inputs
27
a
-
27
n
of the divider
14
.
The divider
14
divides the inputs by “M” and presents a clock signal CLOCK-
00
and a clock signal CLOCK-
90
. The clock signal CLOCK-
00
is presented to an input
30
of feedback divider
15
. The clock signals CLOCK-
00
and CLOCK-
90
are presented to a number of inputs
32
a
-
32
n
of the phase detector
18
. The divider
15
divides the clock signal CLOCK-
00
and presents a divided clock signal DIVIDED at an output
34
. The clock signal DIVIDED is presented to an input
36
of the phase-frequency detector
20
and to an input
38
of the frequency difference detector
16
.
A reference clock signal REFCLK_IN is presented to an input
40
of the phase-frequency detector
20
and an input
42
of the frequency difference detector
16
. The phase-frequency detector
20
compares the signals REFCLK_IN and DIVIDED. A data signal DATA is presented to an input
44
of the phase detector
18
. The phase detector
18
has an output
46
that is connected to the multiplexer
22
. The phase-frequency detector
20
has an output
48
that is connected to the multiplexer
22
. The outputs
46
and
48
present pump-up and pump-down signals.
The multiplexer
22
has an input
50
that receives a control signal LLC. The multiplexer
22
presents a multiplexed signal to an input
52
of the charge pump filter
24
in response to the signal LLC. The frequency difference detector
16
has an output
54
that presents the signal LLC. The frequency difference detector
16
compares the clock signal REFLCK_IN and the clock signal DIVIDED. If the two frequencies are within a certain range, the frequency difference detector
16
toggles the signal LLC. The signal LLC controls the “locking” of the PLL to the clock signal REFCLK_IN or the signal DATA. When the PLL is frequency locked to the clock signal REFCLK_IN, the multiplexer
22
is switched to select the signal DATA. The closed loop of the phase detector
18
then locks to the signal DATA and generates a re-timed data signal RETIMED_DATA and a recovered clock signal RECOVERD_CLK at a number of outputs
56
a
-
56
n
. The circuit
10
requires the implementation of the reference clock signal REFLCK_IN. Furthermore, the circuit
10
also requires the implementation of the frequency difference detector
16
. The circuit
10
implements the half-rate phase detector
18
and a half rate VCO
12
.
Referring to
FIG. 2
, a conventional circuit
60
for performing clock and data recovery in a serial data communication device is shown.
FIG. 3
illustrates a timing diagram of the circuit of FIG.
2
. The circuit
60
implements an analog phase detector
62
and a digital frequency detector
64
. The circuit
60
implements a full-rate clock CLK and corresponding quadrature Q for frequency detection (shown in FIG.
3
). The circuit
60
implements dual loop filter design. The output of the phase detector
62
and the output of the frequency detector
64
are added together by the loop filter
66
(i.e., analog summing). The analog phase detector
62
is not robust in the presence of (i) data dependent jitter and/or (ii) missing data transitions. Hence, the circuit
60
provides a low overall jitter tolerance.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.
The objects, features and advantages of the present invention include providing a circuit configured to recover clock and data signals that may (i) be implemented using lower rate components that may result in higher rate circuits being implemented in existing integrated circuit technologies, (ii) reduce power consumption, and/or (iii) enable reference-free clock and data recovery.


REFERENCES:
patent: 4940952 (1990-07-01), Kegasa
patent: 5739709 (1998-04-01), Banno
patent: 5950115 (1999-09-01), Momtaz et al.
A 1Gb/s CMOS Clock and Data Recovery Circuit, by Hui Wang and Richard Nottenburg, 1999 IEEE International Solid-State Circuits Conference, Feb. 17, 1999, pp. 354-355.
Kamal Dalmia, et al., Data Frequency Detector, Ser. No. 09/471,915, Filed Dec. 23, 1999.
Kamal Dalmia, Digital Phase/Frequency Detector, and Clock Generator and Data Recovery PLL Containing the Same, Ser. No. 09/470,665, Filed Dec. 23, 1999.
Kamal Dalmia, Reference-Free Clock Generator and Data Recovery PLL, Ser. No. 09/471,576, Filed Dec. 23, 1999.

Affiliated with

Also associated with

Rating

Reference-free clock generator and data recovery PLL does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reference-free clock generator and data recovery PLL, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reference-free clock generator and data recovery PLL will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2567527