Reference-free clock generation and data recovery PLL

Details Reference-free clock generation and data recovery PLL Reference-free clock generation and data recovery PLL

1999-12-23

2001-10-30

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S014000, C331S017000, C331S025000, C331SDIG002, C327S156000, C327S157000, C327S159000

Reexamination Certificate

active

06310521

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the recovery of clock signal(s) from a serial input data stream generally and, more particularly, to a method and/or architecture for a linear clock and data recovery phase-lock loop (PLL).
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
a conventional clock and data recovery circuit
10
implemented in a serial data communication device is shown. The circuit
10
comprises an VCO
12
, a divider
14
, a frequency difference detector (FDD)
16
, a phase detector (PD)
18
, a phase-frequency detector (PFD)
20
, a multiplexer
22
and a charge pump filter (CPF)
24
. The VCO
12
generates a full-rate clock signal (i.e., FULL_RATE) at an output
30
. The clock signal FULL_RATE is presented to an input
32
of the divider
14
and to an input
34
of the phase detector
18
. The clock signal FULL_RATE is divided (i.e., by an integer N), by the divider
14
. The divider
14
presents a divided clock signal (i.e., DIVIDED) at an output
36
. The clock signal DIVIDED is presented to an input
38
of the phase-frequency detector
20
and to an input
39
of the frequency difference detector
16
.
The phase-frequency detector
20
also has an input
40
that receives a reference clock signal (i.e., REFCLK_IN). The phase-frequency detector
20
compares the clock signal REFCLK_IN and the clock signal DIVIDED_DOWN. The clock signal REFCLK_IN is presented to an input
42
of the frequency difference detector
16
. The phase detector
18
has an input
44
that receives a signal DATA. The signal DATA operates at a full rate. An output
46
of the phase detector
18
is connected to a first input of the multiplexer
22
. An output
48
of the phase-frequency detector
20
is connected to a second input of the multiplexer
22
. The signals presented at the outputs
46
and
48
are pump-up and pump-down signals.
The multiplexer
22
has an input
50
that receives a control signal LLC. The multiplexer
22
presents a multiplexed signal to an input
52
of the charge pump filter
24
. The multiplexer
22
presents the multiplexed signal in response to the signal LLC. The frequency difference detector
16
presents the signal LLC at an output
54
in response to a comparison between the clock signal REFCLK_IN and the clock signal DIVIDED. If the frequency of the signal REFCLK and the signal DIVIDED are within a certain range, the frequency difference detector
16
toggles the signal LLC. The signal LLC controls (i) the “locking” of the PLL to the clock REFCLK_IN or (ii) the signal DATA. When the PLL is frequency locked to the clock signal REFCLK_IN, the multiplexer
22
is switched to select the rate of the signal DATA. The closed loop with the phase detector
18
then locks to the rate of the signal DATA and generates a signal RETIMED_DATA and a clock signal RECOVERD_CLK. The circuit
10
requires the implementation of the reference clock signal REFLCK_IN of the frequency difference detector
16
.
Referring to
FIG. 2
, a conventional circuit
60
for performing clock and data recovery in a serial data communication device is shown.
FIG. 3
illustrates a timing diagram of the circuit of FIG.
2
. The circuit
60
implements an analog phase detector
62
and a digital frequency detector
64
. The circuit
60
implements a full-rate clock CLK and corresponding quadrature Q for frequency detection (shown in FIG.
1
). The circuit
60
implements dual loop filter design. The output of the phase detector
62
and the output of the frequency detector
64
are added together by the loop filter
66
(i.e., analog summing). The analog phase detector
62
is not robust in the presence of (i) data dependent jitter and/or (ii) missing data transitions. Hence, the circuit
60
provides a low overall jitter tolerance.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having a first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.
The objects, features and advantages of the present invention include providing a circuit that may (i) enable reference-less clock and data recovery, (ii) not require a reference clock generator, (iii) reduce overall circuit die size, (iv) reduce system cost and/or (v) not involve an addition based dual loop architecture.


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A 1Gb/s CMOS Clock and Data Recovery Circuit, by Hui Wang and Richard Nottenburg, 1999 IEEE International Solid-State Circuits Conference, Feb. 17, 1999, pp. 354-355.
Kamal Dalmia et al., Data Frequency Detector, Serial No. 09/471,915, Filed Dec. 23, 1999.
Kamal Dalmia, Reference-Free Clock Generator and Data Recovery, Serial No. 09/471,914, Filed Dec. 23, 1999.
Kamal Dalmia, Digital Phase/Frequency Detector, and Clock Generator and Data Recovery PLL Containing the Same, Serial No. 09/470,665, Filed Dec. 23, 1999.

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