Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-12-26
2003-05-20
Mottola, Steven J. (Department: 2817)
Amplifiers
With periodic switching input-output
C327S124000
Reexamination Certificate
active
06566943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to circuits and methods for amplifying electrical signals. More specifically, the present invention relates to circuits and methods for performing amplification by charge transfer without using a reference voltage.
2. The Prior State of the Art
There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device.
FIG. 1
illustrates a charge transfer amplifier
100
that utilizes an NMOS transistor MN
1
to transfer charge between capacitors CT and CO. The operation of the NMOS charge transfer amplifier
100
will now be described in order to illustrate the basic principle of charge transfer amplification.
The NMOS charge transfer amplifier
100
operates on an amplifier cycle involving three phases including a reset phase, a precharge phase, and an amplify phase.
FIG. 2
is a signal timing diagram for two input signals S
1
and S
2
with respect to the phase that the NMOS charge transfer amplifier
100
is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S
1
and S
2
control corresponding switches /S
1
and /S
2
of FIG.
1
.
FIG. 2
also shows a clock signal CLK. It is apparent that each amplifier cycle takes two complete clock cycles. The reset and precharge phases each take a half clock cycle, and the amplify phase takes a full clock cycle.
Throughout this application, signal S
1
controls switch S
1
(not yet described) and switch /S
1
, and signal S
2
controls switch S
2
(not yet described) and switch /S
2
. Although signal S
3
is not yet described and is not used in conventional charge transfer amplifiers, signal S
3
controls switch S
3
(not yet described). The slash symbol “/” in the value of a switch indicates that the switch is closed when the corresponding control signal is low, and open when the corresponding control signal is high. Conversely, the absence of a slash symbol “/” in the value of a switch indicates that the switch is open when the corresponding control signal is low, and closed when the corresponding control signal is high. Similar nomenclature is used throughout this application for all the switches illustrated and/or described herein.
The cycle begins with the (a) reset phase in which the signal S
1
is low indicating that the switch /S
1
is closed, and in which the signal S
2
is low indicating that the switch /S
2
is closed. Since the switch /S
1
is closed, the upper terminal of capacitor CT (i.e., node
101
) is discharged through the switch /S
1
to voltage Vss. Switch /S
2
is closed indicating that the upper terminal of capacitor CO (i.e., node
102
) is forced to a precharge reference voltage V
PR
.
After the reset phase is the (b) precharge phase in which the signal S
1
is high indicating that switch /S
1
is open, and in which the signal S
2
is low indicating that the switch /S
2
remains closed. Thus, the upper terminal of the capacitor CO (i.e., node
102
) remains charged to the precharge reference voltage V
PR
. This precharge reference voltage V
PR
is high enough that current flows from node
102
to the capacitor CT (and node
101
) through the NMOS transistor MN
1
. For example, if the precharge reference voltage V
PR
is at least equal to the input voltage V
IN
at the gate of the NMOS transistor MN
1
, then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage V
IN
minus the threshold voltage (hereinafter “V
TN
”) of the NMOS transistor MN
1
. At that point, the NMOS transistor MN
1
enters the cutoff region and current flow to the capacitor CT substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of V
PR
while the capacitor CT has a voltage of V
IN
−V
TN
.
After the precharge phase is the (c) amplify phase in which both signals S
1
and S
2
are high indicating that both switches /S
1
and /S
2
are open. During the amplify phase, an incrementally positive input voltage change &Dgr;V
IN
applied at the gate of the NMOS transistor MN
1
will cause the NMOS transistor MN
1
to turn on thereby allowing current to flow through the NMOS transistor MN
1
until the NMOS transistor MN
1
is again cutoff. For small incrementally positive voltage changes &Dgr;V
IN
, the NMOS transistor MN
1
will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node
101
) increases by the incrementally positive voltage change &Dgr;V
IN
. The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change &Dgr;V
IN
times the capacitance C
T
of the capacitor CT.
Since the charge &Dgr;V
IN
×C
T
transferred to the capacitor CT came from node
102
through transistor MN
1
, the charge &Dgr;V
IN
×C
T
was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage V
OUT
will change by &Dgr;V
IN
×(C
T
/C
0
). If the capacitance C
T
is greater than the capacitance C
0
, amplification occurs.
One advantage of the NMOS charge transfer amplifier
100
is that the voltage gain and power consumption may be controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio C
T
/C
0
.
Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd. Although the NMOS charge transfer amplifier
100
has these advantages, there are at least two disadvantages to amplifying using the NMOS charge transfer amplifier
100
.
First, amplification only occurs if the input gate voltage change &Dgr;V
IN
is positive. A negative gate voltage change &Dgr;V
IN
would only cause the NMOS transistor MN
1
to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification.
Second, leakage currents inherent in transistor MN
1
will alter the expected zero-bias (i.e., no input signal) conditions on capacitors CT and CO during the amplify phase. This leakage current may be caused by current undesirably leaking from the source/drain diffusion regions of the NMOS transistor MN
1
into the substrate in which they are formed. Leakage current may also be caused by current flowing between the source and drain terminals of the NMOS transistor MN
1
even though the NMOS transistor MN
1
is substantially cutoff. Either way, this leakage current effectively produces a voltage error at the output terminal that introduces amplification error.
FIG. 3
shows a conventional CMOS charge transfer amplifier
300
that substantially overcomes the above-described limitations of the NMOS charge transfer amplifier
100
. The CMOS charge transfer amplifier
300
includes an NMOS charge transfer amplifier
301
that is similar to the NMOS charge transfer amplifier
100
described above, except that a switch S
1
is provided between the source of the NMOS transistor MN
1
and the charge transfer capacitor CT
L
. This inhibits leakage current in the NMOS transistor MN
1
during the reset phase.
For clarity, the NMOS charge transfer amplifier
301
is shown in
FIG. 3
as being enclosed by a dotted box. The CMOS charge transfer amplifier
300
also includes a partially overlapping PMOS charge transfer amplifier
302
which is shown in
FIG. 3
enclosed by a dashed box for clarity.
AMI Semiconductor Inc.
Mottola Steven J.
Workman & Nydegger & Seeley
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