Reference current/voltage generator having reduced...

Details Reference current/voltage generator having reduced... Reference current/voltage generator having reduced...

2001-06-13

2003-02-18

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000, C323S907000

Reexamination Certificate

active

06522117

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to circuits employed for the generation of reference currents and/or reference voltages, and is particularly directed to a new and improved multi transistor-configured reference current and voltage generator, that is effectively insensitive to variations in power supply voltage and temperature.
BACKGROUND OF THE INVENTION
FIGS. 1
,
2
and
3
respectively depict conventional bipolar, CMOS and BiCMOS current mirror transistor circuits, that are widely used throughout the electronics industry to generate a reference current I
OUT
, that is to be supplied to one or more signal processing circuits of an integrated circuit architecture. ‘Ideally’, this reference current I
OUT
may be defined by equation (1) as:
I
OUT
=
KT
q
*
ln
⁡
(
N
)
R1
=
V
T
*
ln
⁡
(
N
)
R1
(
1
)
Using the bipolar transistor configuration of
FIG. 1
as a representative example of the set of three current generator circuits, the ideal value for its output reference current I
OUT
is based upon the assumption that the current mirror transistors in the two legs of the generator are perfectly matched and that each of the bipolar transistors Q
1
/Q
2
, Q
4
/Q
5
has infinite h
fe
or beta. Namely, if current mirror transistor pair Q
1
and Q
2
are perfectly matched, the collector current through transistor Q
1
in one leg of the circuit is equal to the collector current flowing through transistor Q
2
in the opposing leg. Also, if the current mirror transistor pair Q
4
and Q
5
have infinite h
fe
or beta, the emitter current of transistor Q
4
will be the same as the emitter current of Q
5
, which equals the current through resistor R
1
. The relationship between these currents is summarized in equation (2) as follows:
I
C(Q1)
=I
C(Q2)
=I
C(Q4)
=I
C(Q5)
=I
E(Q4)
=I
E(Q5)
=I
RI
=I
OUT
  (2)
In addition, the voltage drop V
BE(Q
4)
across the base-emitter junction of transistor Q
4
will equal the voltage drop V
BE(Q5)
, plus the voltage drop across resistor R
1
, as set forth in equation (3) as follows:
V
BE(Q4)
=V
BE(Q5)
+I
OUT
*R
1
  (3).
It is well known that the V
BE
of a bipolar transistor is equal to the natural log (ln) of the ratio of its collector-emitter current (I) to the saturation current (Is), as set forth in equation (4).
V
BE
=
KT
q
*
ln
⁡
(
I
I
s
)
=
KT
q
*
ln
⁡
(
I
EmitterArea
⁡
(
Q5
)
*
Js
⁡
(
Q5
)
)
=
V
T
*
ln
⁡
(
I
EmitterArea
⁡
(
Q5
)
*
Js
⁡
(
Q5
)
)
(
4
)
The saturation current (Is) can be rewritten as the emitter area of the transistor multiplied by the saturation current per unit area, or the saturation current density (Js), as also shown in equation (4). Substituting this expression for V
BE
into equation (3) yields equation (5), as follows:
V
T
*
ln
⁡
(
I
EmitterArea
⁡
(
Q4
)
*
Js
⁡
(
Q4
)
)
=
V
T
*
ln
⁡
(
I
EmitterArea
⁡
(
Q5
)
⁢
Js
⁡
(
Q5
)
)
+
I
*
R1
(
5
)
The saturation current densities for transistors with the same doping profiles, formed in the same substrate, and using the same processing steps, will match each other extremely well. As a consequence, it may be inferred that the saturation current density of the transistor Q
4
of the current generator of
FIG. 1
equals the saturation current density of transistor Q
5
, as defined in equation (6).
Js
(Q
4
)=
Js
(Q
5
)=
Js
(npn)  (6)
Equation (7), set forth below, shows that current mirror transistors Q
4
and Q
5
of the current generator of
FIG. 1
are designed such that the ratio of the emitter area of transistor Q
5
to the emitter area of transistor Q
4
is set to a known constant N, defined in equation (7) as:
N=EmitterArea(Q
5
)/EmitterArea(Q
4
)  (7)
Solving equation (5) for I and substituting into equations (6) and (7) yields equation (8), as follows:
I
=
V
T
*
ln
⁢
 
⁢
(
I
*
EmitterArea
⁡
(
Q5
)
*
Js
⁡
(
Q5
)
I
*
EmitterArea
⁡
(
Q4
)
*
Js
⁡
(
Q4
)
)
R1
=
V
T
*
ln
⁡
(
N
)
R1
(
8
)
The sensitivity of a circuit to changes in its power supply voltage is called power supply rejection (PSR). If a circuit had infinite PSR, the output of that circuit would not be affected by changes in the power supply voltage. Although equation (8) implies that the reference current I
OUT
generated by the current mirror transistor circuits of the current generator architecture of
FIGS. 1 through 3
is independent of its power supply voltage Vcc, this equation assumes infinite h
fe
and ‘perfectly matched’ current mirror transistors. In a practical circuit, however, the early voltage effect, shown in the collector current vs. collector-emitter voltage characteristic of
FIG. 4
, will cause mismatches in the current mirrors.
In the bipolar configuration of
FIG. 1
, for example, the early voltages of the two current mirror transistors Q
1
and Q
2
will cause a mismatch in their collector currents, since the collector-emitter voltage V
CE
of transistor Q
1
is not equal to the collector-emitter voltage V
CE
of transistor Q
2
. This difference in collector-emitter voltages is due to the fact that the collector-emitter voltage (V
CE
) of transistor Q
1
equals the power supply voltage rail differential (Vcc−GND) minus the base-emitter voltage (V
BE
) to GND rail differential (e.g., approximately 0.7V) of diode-connected transistor Q
4
.
For a Vcc=5V power supply, therefore, the V
CE
of transistor Q
1
would be approximately equal to (5.0-0.7=) 4.3 volts. Since, however, its associated current mirror transistor Q
2
is diode-connected, the V
CE
of transistor Q
2
equals its V
BE
(0.7V), or about one-sixth of that of transistor Q
1
. This mismatch in the V
CE
voltages of the current mirror transistors Q
1
and Q
2
results in a mismatch in their collector currents (even though the V
BE
voltages of Q
1
and Q
2
are identical).
Such mismatches in the current mirrors will cause the reference current I
OUT
to deviate from the ideal value set forth in Equation (8). This problem is made worse by the fact that the mismatch in the current mirror transistors will change as the power supply voltage varies. Therefore, due to the early voltage effect alone, the reference current I
OUT
generated by the circuits shown in
FIGS. 1 through 3
is not independent of power supply voltage variation.
This can be a significant problem in low voltage applications having reduced power supply ‘headroom’, where high power supply rejection is required. Such headroom limitations are becoming increasingly common as the industry continues to use lower and lower power supply voltages. To solve this problem in a bipolar circuit of the type shown in
FIG. 1
, it has been proposed to couple an auxiliary bias amplifier in circuit with one of the legs of the current generator, as diagrammatically illustrated in
FIG. 5
, and as described, for example, in an article by M. Gunawan et al, entitled: “A Curvature-Corrected Low Voltage Bandgap Reference”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 6, June 1993, pp 667-670, and also in an article by H. Nauta et al, entitled: “New Class of High-Performance PTAT Current Sources,” Electronics Letters, Apr. 25, 1985, Vol. No. 9, pp 384-386.
In the bipolar scheme of
FIG. 5
, the voltages across associated transistors of the two current mirror legs of the current generator are effectively equalized by means of an auxiliary bias amplifier
50
, formed of a current mirror PNP transistor Q
51
and a V
CE
-controlling NPN transistor Q
55
. These two bias amplifier transistors have their collector-emitter current paths connected in parallel with those of transistor pairs Q
52
/Q
53
and Q
56
/Q
57
, of the two current mirror legs that are connected between the power supply rails (Vcc and ground).
The first polarity (PNP) transistor Q
51
of the auxiliary bias amplifier
50
is connected in a diode configuration (having its collector connected to its base), with the base electrode of PNP transistor Q
51
being connected in common to the bases of PNP

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