Reference current generation circuit for multiple bit flash...

Details Reference current generation circuit for multiple bit flash... Reference current generation circuit for multiple bit flash...

2002-08-29

2003-11-04

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S185180

Reexamination Certificate

active

06643176

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention generally relates to a multiple bit flash memory, and more particularly, to a reference current generation circuit for the multiple bit flash memory.
2. Description of Related Art
Flash memory is one kind of the non-volatile memory that performs multiple data program, read and erase operations. Since the data stored in it does not disappear due to the interruption of the power supply and the stored data is easy to be modified via the erase and program operation, it is widely used now in electronic equipment such as the personal computer.
The typical flash memory comprises a plurality of flash cells, and each flash cell generally stores a bit of data. The doped polycrystalline silicon is used to form a floating gate and a control gate of the flash memory. The floating gate and the control gate are isolated by a dielectric layer, and the floating gate and the substrate are isolated by a tunnel oxide. When the flash cells are performing the program/erase operation, a bias voltage is applied onto the control gate and drain to inject electrons into the floating gate or pull out electrons from the floating gate. When reading data from the flash cells, a word-line voltage is applied onto the control gate. The electric status of the floating gate impacts the ON/OFF status of the channel below it, and the ON/OFF status of the channel is used to determine whether the data is “0” or “1”.
In line with progress in semiconductor technology and the increase in the requirements for flash memory capacity, a multiple bit flash memory has been developed, and each flash cell stores a data that has more than two bits. Therefore, when reading the data stored in the flash cells, the current that is read has to compare with a reference current to determine the value of the stored data.
FIG. 1
schematically shows a sketch map of the threshold voltage distribution for the flash memory's 2-bit flash cell. Where the abscissa represents the magnitude of the threshold voltage Vth, and the ordinate represents the quantity of each threshold voltage Vth's flash cell. Moreover, the quantity distribution is like a gauss distribution as shown in the diagram. From
FIG. 1
, when erasing the flash cells, the threshold voltage Vth is below EV; when programming a “01” data value into the flash memory, the threshold voltage Vth is between PV
1
and R
2
when programming a “10” data value into the flash memory, the threshold voltage Vth is between PV
2
and R
3
, and when programming an “11” data value into the flash memory, the threshold voltage Vth is above PV
3
. Therefore, the word-line voltage EV is applied onto the control gate when erasing the flash cells, and whether the erasing operation is completed or not is determined via the read current; when programming “01”, “10”, and “11” data values into the flash cells, the word-line voltage PV
1
, PV
2
, and PV
3
are respectively applied onto the control gate, and whether the programming operation is completed or not is determined via the read current. When reading the data value stored in the flash cells, the word-line voltages R
1
, R
2
, and R
3
are respectively applied onto the control gate, and the data value is determined via the read current. Moreover, the read current is compared with a reference current to determine the data value that is read.
The conventional reference current generation circuit used to achieve the objective mentioned above applies the boosted word-line voltages (BWLV) with different levels onto gates of different reference cells. When the 2-bit flash cell mentioned above is exemplified, since totally there are seven different levels for the word-line voltages for the erase verify, the program verify, and the read operations, they are EV, PV
1
, PV
2
, PV
3
, R
1
, R
2
, and R
3
, so that the boosted word-line voltages with seven different levels are needed for implementation. For example, the boosted word-line voltages with 15 different levels are needed to implement the 3-bit flash cell. Since each boosted word-line voltage has different variance when it is impacted by the variance of the temperature and the power voltage Vcc, each reference current generated by the reference generation circuit via this method has different drift along with the variance of the temperature and the power voltage Vcc.
SUMMARY OF INVENTION
Therefore, the present invention provides a reference current generation circuit, it can solve the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.
In order to achieve the objective mentioned above and others, the present invention provides a reference current generation circuit and it is suitable for a multiple bit flash memory. The reference current generation circuit comprises a plurality of reference current generation units, and each reference current generation unit comprises a load, a voltage dividing circuit, and a reference cell. The load comprises a first connection terminal and a second connection terminal, wherein the first connection terminal couples to an operating power, the second connection terminal couples to a first source/drain of the reference cell, the second source/drain is grounded, the gate of the reference cell couples to a gate voltage, and the gate voltage is obtained from dividing a boosted word-line voltage coupled to the voltage dividing circuit, The voltage dividing circuit of each reference current generation unit couples to the same boosted word-line voltage, and the gate voltage obtained from the voltage dividing of the voltage dividing circuit is varied based on the magnitude of the reference current needed to be generated by the reference current generation circuit.
In a preferred embodiment of the present invention, the reference cell is a dummy cell, and the so-called dummy cell is formed by merging the floating gate and the control gate of the multiple bit flash memory's flash cell having the same structure together. Moreover, the voltage dividing circuit may be made of a plurality of resistors coupled in serial, wherein for ease of handling the reference cell characteristic, the dimensions of the gate length and the gate width of the reference cell should be made greater than the dimensions of the gate length and the gate width of the multiple bit flash memory's flash cell. For example, the dimensions of the gate length and the gate width of the reference cell should be designed as 1 &mgr;m.
Moreover, in order to further improve characteristics of the reference cells, the reference cells whose quantity is greater than the quantity needed by each reference current generation unit are formed in the same bank, and one or more than one reference cells are used to generate the reference current. When a plurality of the same reference cells in the same bank are used to generate the reference current, all the same reference cells used are tightly coupled in parallel to generate the reference current.
From the description mentioned above, since the reference current generation circuit provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of a different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.


REFERENCES:
patent: 6434049 (2002-08-01), Trivedi et al.

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