Reference current generating circuit of multiple bit flash...

Details Reference current generating circuit of multiple bit flash... Reference current generating circuit of multiple bit flash...

2002-09-12

2003-12-16

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S189090

Reexamination Certificate

active

06665212

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a multiple bit flash memory. More particularly, the present invention relates to the reference current generating circuit of a multiple bit flash memory.
2. Description of Related Art
Flash memory is a multiple program, read and erase non-volatile memory. Since stored data will not disappear after removing the power and content can be easily erased and changed through programming, most electronic equipment such as the personal computer adopts this device.
A typical flash memory includes a large number of flash memory cells with each flash memory cell capable of holding one bit of data. In general, a flash memory cell structure has a floating gate and a control gate made from doped polysilicon. The floating gate and the control gate are isolated from each other through a dielectric layer. Moreover, the floating gate is isolated from the substrate through a tunnel oxide layer. To write data into or erase data from a flash memory cell, a bias voltage is applied to the control gate and the drain terminal so that electrons are injected into the floating gate or electrons are pulled out from the floating gate. To read data from the flash memory cell, a word line voltage is applied to the control gate. The charge-up state of the floating gate has a direct effect on the on/off state of the channel underneath. According to the on/off state of the channel, logic state such as logic “0” or “1” in the flash memory cell can be determined.
Following the rapid progress in technologies and an impending demand for a flash memory with a higher storage capacity, a type of multiple bit flash memory has been developed. In other words, each flash memory cell is capable of holding at least two bits of data. To read data from this type of flash memory cell, the read-out current must be compared with a reference current before the value actually stored inside the memory cell can be determined.
FIG. 1
is a threshold voltage distribution diagram of a conventional 2-bit flash memory cell. In
FIG. 1
, the horizontal axis represents size of the threshold voltage V
th
while the vertical axis represents the number of flash memory cells having the threshold voltage V
th
. In general, the number of flash memory cells within a definite range of threshold voltage V
th
will follow a Gaussian distribution as shown in FIG.
1
. To erase data from the flash memory cell, the threshold voltage V
th
is below EV. To write a data value “01” into the flash memory cell, the threshold voltage V
th
is between PV
1
to below R
2
. To write a data value “10” into the flash memory cell, the threshold voltage V
th
is between PV
2
and below R
3
. Finally, to write a data value “11” into the flash memory cell, the threshold voltage V
th
is above PV
3
. Hence, a word line voltage EV is applied to the control gate to erase data from the flash memory cell and the read-out current is gauged to determine if the erasing operation is complete. To write data values “01”, “10”, “11” into the flash memory cell, word line voltages PV
1
, PV
2
and PV
3
are applied to the control gate respectively and the read-out current is gauged to determine if the write-in operation is complete. To read stored data value from the flash memory cell, word line voltages R
1
, R
2
and R
3
are applied to the control gate respectively and the read-out current is gauged to determine if the read-out operation is complete. Meanwhile, the read-out current and a reference current produced by a reference current generation circuit are compared to determine the actual read-out data value.
In general, a conventional reference current generation circuit generates a reference current through the application of boosted word-line voltage (BWLV) at different levels to the gate terminal of different reference cells. For example, the aforementioned 2-bit flash memory cell must include EV, PV
1
, PV
2
, PV
3
, R
1
, R
2
and R
3
. In other words, altogether 7 different levels of word line voltages and hence 7 different boosted word-line voltages are required for the execution of erase verify, program verify and read operations. If a 3-bit flash memory cell is used, boosted word-line voltage at 15 different levels are required. Since various boosted word-line voltages may change in response to temperature or power source voltage V
CC
, various reference currents produced by the reference current generation circuit are likely to shift in value in accordance to any change in temperature and source voltage V
cc
.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a reference current generation circuit capable of reducing current shift due to a change in temperature and source voltage V
CC
.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a reference current generation circuit for a multiple bit flash memory. The reference current generation circuit includes a plurality of reference current generation units with each reference current generation unit comprising a loading and a reference memory cell. The loading has a first terminal and a second terminal. The first terminal of the loading is connected to an operating power source and the second terminal of the loading is connected a first source/drain terminal of the reference memory cell. A second source/drain terminal of the reference memory cell is connected to a ground terminal and the gate terminal of the reference memory cell is connected to a boosted word-line voltage. The substrate of the reference memory cell is connected to a substrate voltage. The gate terminal of each reference current generation unit is connected to an identical boosted word-line voltage and the substrate voltage to the substrate of each reference current generation unit will differ according to the size of reference current produced by the reference current generation unit.
In one embodiment of this invention, the reference memory cell is a dummy cell. The so-called dummy cell is formed by joining together the floating gates and control gates of flash memory cells, each one having an identical structure, inside a multiple bit flash memory cell. To realize the properties of a reference memory cell in full, the gate of the reference memory cell has a length and width greater than that of the flash memory cell of the multiple bit flash memory. For example, the length and width of the gate of the reference memory cell has a dimension 1 &mgr;m×1 &mgr;m by design.
To improve the properties of reference memory cells even further, each reference memory cell in excess of the number required to form the reference current generation unit is fabricated inside the same layout bank. The reference current is generated using a single reference memory cell or a plurality of identical reference memory cells. Furthermore, to produce the reference current using identical reference memory cells within the same bank, all the reference memory cells are connected together in parallel.
According to the aforementioned explanation, this invention provides a reference current generation circuit that applies an identical boosted word-line voltage to the gate terminal of different reference memory cells. Moreover, different substrate voltages are applied to the substrate of reference memory cells. Hence, the degree of shifting of the reference current due to a change in temperatures and/or the power source voltage V
CC
is greatly reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6434049 (2002-08-01), Trivedi et al.

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