Reference clock generation system and device

Details Reference clock generation system and device Reference clock generation system and device

2002-02-15

2004-03-09

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S291000, C375S376000, C331SDIG002

Reexamination Certificate

active

06703876

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a clock generation system for generating, from a first clock having a given clock frequency, a second clock having a second frequency of predetermined frequency ratio relative to the first clock frequency.
BACKGROUND OF THE INVENTION
It has been conventional in the art of digital TV, DVHS, DVD, and game machines to generate from a first clock having a given frequency a second reference clock having a second frequency.
For example, in a HIGH VISION TV signal system, a desired reference clock of 74.25 MHz is obtained from an externally input 54 MHz (13.5 MHz×4) clock by stepping up (or stepping down in certain cases) the given clock frequency with a desired ratio (e.g. 54 MHz×11/8=74.25 MHz). The external clock of 54 MHz is generated from a characteristic frequency (13.5 MHz) of quartz oscillator (13.5 MHz×4).
In the HIGH VISION TV signal system, synchronization signals are provided for conversion of the HIGH VISION signal (60 Hz) to NTSC-TV signal (59.94 Hz) and vise versa. The frequencies of these synchronization signals have a ratio of 1001:1000. These synchronization signals can be obtained by a phase locked loop (PLL) circuit.
FIG. 1
shows a typical reference clock generation circuit using a conventional PLL circuit. As seen in
FIG. 1
, the PLL circuit is provided with a first reference clock F
1
of 54 MHz and converts the signal into a second reference clock by frequency converting 54 MHz to 54/1.001 MHz.
To do this a first frequency divider
1
divides the frequency 54 MHz of the input signal to 1/1001 and uses it as a comparison signal P
1
input to one terminal of a phase comparator
3
, as shown in
FIG. 1. A
second frequency divider
2
further divides the frequency of the output of the PLL circuit to 1/1000 to generate another comparison signal P
2
for the phase comparator
3
. The phase comparator
3
compares the two input P
1
and P
2
to generate a comparison output associated with the difference in phase between them. The comparison output is smoothed by a low-pass filter (LPF)
4
to generate a control signal for controlling a voltage controlled oscillator (VCO)
5
. The VCO
5
is controlled by the input control signal such that the two signals input to the phase comparator
3
match in frequency and in phase. Since the loop gain of the PLL circuit is large, residual system deviation thereof is negligibly small, so that the second reference clock F
2
generates an output having 54×1000/1001 MHz in accordance with the division ratio between the first and the second frequency dividers
1
and
2
, respectively.
The signal-to-noise (S/N) ratio of the PLL circuit of
FIG. 1
can be obtained based on a well known noise theory, as follow. The S/N ratio is improved by a factor of 20log1001 [dB] in the first frequency division of the first reference clock F
1
by 1001. Thus, the S/N ratio of the output of the first frequency divider
1
is theoretically given by the S/N ratio of the first reference clock F
1
plus 20log1001 [dB]. Hence, assuming that the first reference clock F
1
has an S/N ratio of 80 [dB], the S/N ratio of the output of the first frequency divider
1
is about (80+60)=140 [dB].
However, since the PLL circuit is formed on an integrated circuit (IC), the PLL circuit operates on the noise floor of the IC and hence the S/N ratio of the PLL circuit cannot be better than the S/N ratio of the noise floor. The S/N ratio of the noise floor is determined mainly by the fluctuations of the source voltage, which is normally about 90 [dB]. In other words, the S/N ratio of the PLL circuit is limited by the S/N ratio of the noise floor. Consequently, the maximum possible S/N ratio of the output of the first frequency divider
1
, i.e. the comparison input signal P
1
of the phase comparator
3
, is at best 90 [dB].
The S/N ratio of the other comparison input P
2
of the phase comparator
3
is also 90 [dB], since the S/N ratio of the two comparison inputs P
1
and P
2
of the phase comparator
3
are the same.
The input to the second frequency divider
2
, i.e. the second reference clock F
2
, is stepped up in frequency by a factor of 1000, so that the S/N ratio of the input is stepped down by 20log1000 [dB]. Consequently, the second reference clock F
2
has S/N ratio equal to the S/N ratio of the comparison input P
2
minus 20log1000 [dB] or 30 [dB].
In this way, although conventional PLL circuits can generate a second reference clock F
2
having a desired frequency equal to the frequency of the first reference clock F
1
multiplied by a predetermined ratio (e.g. 1000/1001), the S/N ratio of the second reference clock F
2
is disadvantageously reduced to as low as 30 [dB]. Such low S/N ratio is a serious problem in video clock technology, since video clocks are generally required to have S/N ratio of at least 50 [dB].
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a clock generation system, and a clock generation device as well, comprising PLL circuits adapted to generate from a first clock having a first clock frequency a second reference clock having a second clock frequency which is related to the first clock frequency by a predetermined ratio, such that the second clock has a sufficiently high S/N ratio irrespective of the limitation by the noise floor of the system.
To accomplish the object, the invention provide a clock generation system for generating from a given first clock having a first clock frequency a second clock having a second clock frequency which is related to the first clock frequency by a predetermined ratio, the clock generation system comprising:
a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock, each of said PLL circuit stages having
a first frequency divider for frequency dividing the clock signal input thereto;
a second frequency divider for frequency dividing the output of said PLL circuit stage;
a phase comparator for comparing said frequency divided output of said first frequency divider and the frequency divided output of said second frequency divider;
a filter for filtering the output of said comparator; and
a voltage controlled oscillator controlled by the output of said filter for supplying said second frequency divider with a signal having a controlled frequency, wherein
said first and second frequency dividers are adapted to perform frequency division assigned to said PLL circuit stage.
In view of the fact that the S/N ratio of a PLL circuit increases with the frequency division ratio, hence decreases with the step-up ratio, and that the maximum S/N ratio is limited by the noise floor associated with the PLL circuit, the multiplicity of series PLL circuit stages are provided in such a way that the stages have distributed frequency division ratios to altogether attain a desired S/N ratio even under the noise floor. Such distribution of frequency division ratios ensures circumvention of the limitation of the maximum S/N ratio by the noise floor, thereby allowing the conversion of the first clock into the second clock having a sufficiently large S/N ratio.
In the inventive multi-staged PLL circuit, the frequency division ratios of the first and the second frequency dividers are set, at least in the stages other than the first, such that their S/N ratios are smaller than that of the noise floor.
Hence, except for the first stage where the S/N ratio depends largely on the S/N ratio of first clock input thereto, noise floor limitation can be circumvented in the subsequent stages. Given the S/N ratio of the first clock, it is possible to configure all the PLL circuit stages to circumvent the noise floor limitation.
In the example shown herei

Affiliated with

Also associated with

Rating

Reference clock generation system and device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reference clock generation system and device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reference clock generation system and device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3241716